Towards a standard methodology for reporting D2D PHY metrics
- Bapi Vinnakota, LBNL, Open Compute Project
- Bill Chen, ASE
- Elad Alon, Blue Cheetah
- Quinn Jacobson, CMU Silicon Valley
- Ramin Farjadrad, Eliyan
- Shahab Ardalan, Enosemi
- Andy Heinig, Fraunhofer Institute IIS EAS
- Majid Foodeei, Kandou
- John Shalf, Lawrence Berkeley National Lab
On Monday October 16th, 2023, the OCP’s Open Domain Specific Architecture Project (ODSA) 2023 Technical Workshop on Die-to-Die (D2D) Interfaces took place at Carnegie Mellon University Silicon Valley (CMU). A bit of a self-serving take, but the event was a fantastic way to spend a day. A focused technical agenda, expert participants (presenters and audience) made for a really engaging workshop, an experience worth repeating. Thanks to Quinn and CMU for being gracious hosts, Eliyan for the food/refreshments and to Shahab and Quinn for getting the agenda together and moderating the day.
We had presentations on standards (BoW - Elad from Blue Cheetah, UCIe - Letizia from Alphawave Semi), standards-based, UCIe (Synopsys, Alphawave), BoW/UCIe (Blue Cheetah, Eliyan, Fraunhofer), OIF (Kandou) and proprietary PHYs (GUC), Optical (Intel, Ayar and Enosemi) applications (d-Matrix) and chiplet market (Yole research), a metrics methodology discussion and a panel with participants from ASE, LBNL, Marvell, Microchip and Samsung to close the day. One of the attendees (Sam from BAH) took some incredible notes, even of the very animated panel discussion (Anu, Bill, John, Kevin, Mark) and was kind enough to share. We (Anu, Majid, Danesh and Bapi) added a little bit of our own to his.
There was substantial interest in the motivation for the workshop, to help users evaluating PHYs by creating a standard methodology to report PHY performance and cost. A group has already started work on the whitepaper and aims to report out in Q1 2024. We invite you to join this effort, meeting weekly on Tuesdays at 9:30 AM Pacific.
The day’s presentations, recording and notes are available here. The rest of this article is our takeaways from the workshop, not a summary.
The workshop reinforced one primary fact - the open chiplet economy is here to stay. Every presenter had already developed a D2D PHY and shared measured (rather than simulated) performance data. The aggregate investment in creating these PHYs is substantial and couldn’t have happened without the perception and anticipation of significant demand. The potential scaling, time to market and RoI advantages on offer mean chiplets are going to spread to more companies developing ASICs and across more applications. Compared to even three years ago, today the availability of field-validated PHY IP means there’s a rich set of vendors, i.e. a real open chiplet economy, to help more companies develop chiplets. There is a lot of interest in an eventual ability to easily integrate chiplets from multiple vendors. Thanks to the incredible job done by the UCIe consortium in spreading awareness of D2D standards, there’s great optimism that standards can enable that future for chiplets.
In practice, chiplet use is still largely top-down application-driven, and is likely to stay this way for at least the immediate future, with AI as the dominant application. What that implies is that all aspects of a chiplet, including the D2D interface are application driven, resulting in a constant tension between the requirements of an application and the desire for a single unifying standard. If a standard doesn’t provide the flexibility, performance or cost required by an application, designers are still ready to resort to proprietary PHYs.
In order to be designed in, standards have no choice but to allow the flexibility to adapt to application demands and hence some splintering of standardizations into islands of interoperability is inevitable. For example, UCIe’s streaming mode is the most popular UCIe mode because it can be customized most closely to meet application requirements. However, streaming mode interoperability above the PHY layer is largely an open issue. Bunch of Wires is a sparer specification and deliberately leaves room for customization, but also specifies less on PHY layer interoperability. And there might yet be demand for more specialized standards for memory access and co-packaged optics.
The optimism on standards is accompanied by a growing recognition that PHY standards are just a part of the story, confirmed by discussions through the day. Chiplets will likely require open standards and support for logical integration, business and supply chain workflows, for EDA tool flows, for advanced packaging and other flows needed to make a product that integrates chiplets from multiple vendors. The market still needs to develop a collective understanding about “how much” interoperability we need, where and when. Education and support in the form of tools and resources, such as the methodology white paper, is essential to help grow the Open Chiplet Economy.
Some other interesting standalone observations:
- Elad proposed a new way to classify PHYs that was well received.
- We still don’t have good metrics on chiplet economics across vendors, especially on integration complexity and towards the upside.
- A collection of large-enough but small markets - auto, ADAS, HPC might actually drive open chiplets
- Interop across vendors may be easier on standard packaging than with advanced packaging.
- 3D chiplet interconnects may “never” be standardized because cross-foundry 3D is unlikely for a while.
- Optical trending to a cost being low enough to be manageable and at a time when there is a clear application demand from large models.
Please join one of the OCP work streams working on the Open Chiplet Economy - on the issues discussed above and more around chiplets. The ODSA’s mailing list can be accessed at https://ocp-all.groups.io/g/OCP-ODSA. Join the Open Chiplet Economy session at the Chiplet Summit in February.