IT Infrastructure

The field of heterogeneous chiplet systems, particularly in advanced packaging, has seen significant growth and interest recently. This surge is driven by the evolution of chiplet design and packaging manufacturing, which offers innovative solutions to overcome…

This specification describes Revision A (or Rev A) of the transaction and link layers for ODSA die-to-die (D2D) communication. The transaction and link layers form two parts of a layered architecture using the ODSA bunch-of-wires (BoW)…

The scope of this document has several levels. The specification of the BoW interface includes these requirements: The specification includes recommendations for these elements: Bunch of Wires (BoW) PHY Specification 2.0

This document defines the technical specifications for the OpenHBI-L under OCP Server project, ODSA subproject. Scope of OpenHBI-L includes but not limited to the following: OpenHBI-L Specification for Laminate Substrate V1.0 Specification

Low Latency Ethernet Chiplet up to 100G data rates Low Latency PCIe Gen 5 Chiplet Low latency LP DDR5 Chiplet FPGA Chiplet with UCIe 

Low Latency Ethernet Chiplet up to 100G data rates Low Latency PCIe Gen 5 Chiplet Low latency LP DDR5 Chiplet FPGA Chiplet with UCIe 

Credo designs SerDes IP that optimally balances performance, power and manufacturing process costs and risks. Our unique, patented mixed signal and DSP architectures are the foundation for our high performance and low power SerDes technology. The architectural approach…

Credo’s SerDes Intellectual Property (IP) is designed for the easy SOC integration from tens to hundreds of SerDes lanes.

Synopsys’ complete Universal Chiplet Interconnect Express (UCIe) IP solution, including controller, PHY, and verification IP, offers high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package. The PHY has achieved silicon success on multiple advanced foundry…

Synopsys 3DIC Compiler, a unified exploration-to-signoff platform, delivers the highest levels of design efficiency for capacity and performance. It leverages a single data-model to integrate design, die-to-die routing, test and silicon lifecycle management, native system analysis,…