Credo designs SerDes IP that optimally balances performance, power and manufacturing process costs and risks. Our unique, patented mixed signal and DSP architectures are the foundation for our high performance and low power SerDes technology.
The architectural approach taken by Credo has enabled us to design in mature fabrication processes yet deliver leading-edge performance and power. Credo was the first to deliver 56G NRZ in 40nm, 56G PAM4 and 112G PAM4 in 28nm.
Features
- Switch Fabric ASIC
- AI ASIC
- Machine Learning ASIC
- CPO Support
Parameters – 112G per Lane SerDes
- Retimer Function
- 32 lanes with PAM4, LR on the Line Side
- Low-power XSR on the Host Side
