The field of heterogeneous chiplet systems, particularly in advanced packaging, has seen significant growth and interest recently. This surge is driven by the evolution of chiplet design and packaging manufacturing, which offers innovative solutions to overcome challenges posed by the slowing progression of Moore’s Law and the limitations of large, monolithic System-on-Chips (SoCs).
This whitepaper delves into the entire lifecycle of designing a chiplet-based system. It begins with System Planning and Co-Design, moves through System Implementation, and concludes with System Verification and Signoff. The document serves as an essential guide for developing a comprehensive and robust design flow and methodology tailored for the new era of chiplet systems.
A key focus of this whitepaper is highlighting the unique subflows required for chiplet-based design, such as System Technology Co-Optimization (STCO), Thermal Analysis, Mechanical Analysis, and more. These are integral to addressing the specific needs of chiplet-based systems and expand upon conventional chip-level subflows like Power Modeling, Signal Integrity, Timing Analysis, and Design For Test (DFT).
Proposed Standardization of Chiplet Models for Hetergenerous Integration Whitepaper
