Credo’s SerDes Intellectual Property (IP) is designed for the easy SOC integration from tens to hundreds of SerDes lanes.
- Supported on process nodes from 28nm to 3nm
- XSR to LR (a few dB to 40 dB) bump-to-bump insertion loss support
- Multi-rate support for 56Gbps to 112Gbps PAM4 and lower rate NRZ
- Integrated PLLs
- Robust clock distribution architecture
- Advanced mixed signal analog and DSP equalization architectures
- Fully adaptive and programmable equalization
- Auto-Negotiation
- Link Training
- Robust clock data recovery
- Complete built-in diagnostics
