Chiplets & Intellectual Property

The Cadence UltraLink Die-to-Die (D2D) PHY enables SoC providers to deliver more customized solutions that offer higher performance and yields while also shortening development cycles and reducing costs through greater IP reuse.

The Ayar Labs optical I/O solution is a small-footprint, low-power, high-throughput alternative to copper backplane and pluggable optics-based interconnect solutions. Combining silicon photonics with standard CMOS manufacturing processes, Ayar Labs’ optical I/O solution delivers up to…

Low Latency Ethernet Chiplet up to 100G data rates Low Latency PCIe Gen 5 Chiplet Low latency LP DDR5 Chiplet FPGA Chiplet with UCIe 

Welcome to the Chiplet.US Catalog by Palo Alto Electron. Explore our extensive range of cutting-edge chiplets and heterogeneous components designed to meet the demands of modern semiconductor technology. Our catalog offers advanced chiplets as well as…

Achronix Speedcore eFPGA IP is an advanced embedded FPGA technology engineered for seamless integration into custom ASICs and SoCs, particularly within chiplet architectures. Speedcore eFPGA IP provides unmatched flexibility, enabling on-chip reconfigurability to adapt to evolving…

Synopsys 3DIO Platform is a specialized IO for multi-die integration. It offers versatile solutions for system-on-chip (SoC) designers to implement tunable, integrated multi-die design structures targeting HPC (AI), GPU, CPU, and mobile applications. The optimal area…

Synopsys offers a complete HBM IP solution, including controller, PHY and verification IP, to meet the essential high-bandwidth and low-power memory requirements of system-on-chip (SoC) designs targeting high-performance computing, AI and graphics applications. The IP, supporting…

Synopsys’ complete Universal Chiplet Interconnect Express (UCIe) IP solution, including controller, PHY, and verification IP, offers high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package. The PHY has achieved silicon success on multiple advanced foundry…

Credo’s SerDes Intellectual Property (IP) is designed for the easy SOC integration from tens to hundreds of SerDes lanes.

Credo designs SerDes IP that optimally balances performance, power and manufacturing process costs and risks. Our unique, patented mixed signal and DSP architectures are the foundation for our high performance and low power SerDes technology. The architectural approach…