Chiplets & Intellectual Property

The AMI® Developer Program for Arm® Total Design (ATD) provides early access to essential firmware and tools to accelerate custom silicon development based on Arm Neoverse® Compute Subsystem (CSS) chiplet architecture. Tailored for ATD ecosystem partners,…

Since its debut as the industry’s first UEFI BIOS in production, InsydeH2O® has been at the forefront of platform innovation—continuously evolving to support the latest industry standards and emerging platform technologies. Through collaboration with partners in…

Insyde Software, an industry leader in system firmware and engineering services, brings its deep expertise to the OCP Chiplet Marketplace with insydeICE™, a developer-focused enablement program designed to accelerate Arm Neoverse CSS-based chiplet designs. insydeICE™ provides:…

Astera Labs Intelligent Connectivity Platform seamlessly integrates high-speed connectivity with a combination of I/O chiplets, ICs, Modules, Boards, and COSMOS (COnnectivity System Management and Optimization Software) suite for unparalleled data center visibility and optimized performance. This…

AI CPU Chiplet Key architectural objectives include: This Chiplet-based design aims to reduce overall power consumption in AI data centers while maintaining high compute density and performance. The collaborative effort highlights the synergy between advanced semiconductor…

REBEL-Quad is an advanced AI SoC built on a UCIe-Advanced chiplet architecture, designed to meet the extreme compute and memory demands of serving frontier LLMs at massive scale for hyperscalers, AI data centers, and enterprises. It…

AMI OnSil™ is AMI’s Silicon Firmware that provides advanced modules for faster customization of SoC design with added features and drivers to support Arm’s SCP, MCP, LCP, RSE, and TF-A technologies. Additionally, customers can also take advantage…

Arm Neoverse Compute Subsystems (CSS) are designed to help Arm partner deliver the latest Neoverse technology to market more quickly, with less risk, and with more customer-defined differentiation than they could do so previously. Neoverse CSS…

The Cadence UCIe™ PHY is a high-bandwidth, low-power and low-latency die-to-die solution that enables multi-die system in package integration for high performance compute, AI/ML, 5G, automotive and networking applications. 

Cadence PHY IP for high-bandwidth memory (HBM) is supports high-performance 3D-stacked DRAM system-in-package (SiP) development.