Description:
AI infrastructure is evolving to support increasingly diverse training, distributed inference, reasoning, and agentic AI workloads. Longer context windows, KV-cache growth, and continuous inference are creating new requirements for memory access, storage integration, and data movement across compute, memory, storage, and networking. As a result, networking has become a key determinant of accelerator utilization, latency, job completion time, and overall system efficiency.
Join AMD and Dell’Oro for a technical discussion on how front-end, scale-up, and scale-out networks are evolving to meet these demands. We’ll examine DPU offload, NVMe-oF and KV-cache architectures, scale-up fabrics designed to enable larger accelerator memory domains, and programmable Ethernet-based scale-out networks optimized for AI communication patterns.
The conversation will explore engineering tradeoffs around congestion management, traffic distribution, transport protocols, resiliency, telemetry, and programmable networking with AMD Pensando™ P4 programmable architecture. We’ll also discuss how infrastructure responsibilities are shifting between CPUs, DPUs, AI NICs, and switches, and how network architecture impacts GPU utilization, infrastructure efficiency, and the performance of large-scale AI systems.
Who should attend?
Data Center and AI Infrastructure Architects, Network Architects and Engineers, Hyperscalers, Cloud and NeoCloud Service Providers, AI Infrastructure Providers, Networking and Silicon Vendors, Enterprise IT Leaders, and CIOs, CTOs, VPs and Directors responsible for AI, networking, cloud, and data center infrastructure.
What will you learn?
- AI networking market overview and key trends shaping next-generation AI infrastructure
- Evolving front-end networking requirements for distributed inference, KV-cache movement, and data-intensive AI workloads
- Scale-up architecture considerations for resiliency, fault isolation, and recovery within rack-scale AI systems
- Programmable AI NICs and open Ethernet transports for high-performance scale-out networking across large AI clusters
- The role of programmability and open networking in adapting infrastructure as AI workloads, transports, and system requirements evolve
- AMD Helios as an open rack-scale architecture integrating AMD EPYC™ CPUs, AMD Instinct™ accelerators, and AMD Pensando™ networking.
Speakers:
Shane Corban
Senior Director of Technical Marketing, AMD
Shane Corban is a Senior Director of Technical Marketing at AMD’s Network Technology Solutions Group (NTSG), where he specializes in AMD’s data processing units (DPUs), AI Networking, and smart switch product lines. Before joining AMD, Shane spent 14 years at Cisco, focusing on product management and engineering for Nexus data center switching products. He also held engineering positions at Brocade and Sun/Oracle prior to his time at Cisco.
Sameh Boujelbene
Vice President, Data Center Switch, AI Back-end Networks and Front-end Networks, Dell’Oro Group
Sameh Boujelbene joined Dell’Oro Group in 2011 and leads market research for Data Center Switch—AI Back-end Networks and Front-end Networks. Her front-end switch forecasts since 2020 have been highly accurate. She also developed research on Ethernet Adapters, Servers, and Campus Switches. Ms. Boujelbene has published articles and been cited in various industry and trade publications, and she is a frequent speaker at industry conferences and events.
Cliff Grossner, Ph.D.
Chief Innovation Officer, Open Compute Project Foundation (OCP)
At the Open Compute Project Foundation, Dr. Grossner leads its market intelligence function and is responsible for driving awareness of OCP, training and certification programs, and guiding inventors presenting their early-stage company ideas to potential investors. Dr. Grossner has more than 25 years of telecommunications industry experience encompassing scientific research, market analysis, corporate and product strategy, product management and marketing. His current interests include IT Ecosystems from cloud to the edge looking at the equipment [servers, IT networking and storage] and software, and physical infrastructure [power and cooling] needed for computation, with a focus on edge computing, silicon components included in IT equipment including coprocessors for AI and ML. Previously, Dr. Grossner was head of the Cloud and Data Center Research Practice, which he launched at Infonetics research and followed through transitions to IHS, IHS Markit and Informa Group. Prior to Infonetics, he held senior positions, including heading strategic marketing for Alcatel-Lucent’s enterprise network business, tenures at Bell Labs, several startups and Nortel. He earned his Ph.D. at McGill University, and his Master of Science in Computer Science at Concordia University, winning national scholarships to support his graduate work. He holds more than 10 patents in computer networking, networking embedded security and telecommunications applications.