A Chiplet interconnection specification optimized for maximum applicability enabling low cost and energy efficient implementations.
Today, the OCP Foundation, the nonprofit organization bringing hyperscale innovations to all, announced the release of the Bunch of Wires (BoW) specification for Chiplet interconnect. The BoW specification represents a next step in the OCP Open Domain Specific Architecture (ODSA) Project's march towards establishing an open Chiplet ecosystem as a catalyst for a new silicon market place and integrated circuit supply chain model. BoW specifies a physical layer (PHY) optimized for System on a Chip (SoC) disaggregation, and complements OCP ODSA Open High Bandwidth Interconnect (OpenHBI) PHY specification targeting High Bandwidth Memory and other parallel bandwidth intensive use cases.
“The demand for specialized silicon has been increasing steadily due to workload diversity, such as with the adoption of AI and ML, and we expect this trend to continue for several years. In response to this demand the OCP recognizes that it must be a catalyst to establish open and standardized Chiplet ecosystems and new markets by investing in Chiplet interconnect technology that will enable composable silicon. The release of the BoW specification is an important step in this direction. At the OCP we expect to increase our efforts on developing supply chain models for composable silicon," said Bill Carter, CTO for the OCP Foundation.
The ODSA BoW PHY specification is optimized for both commodity (organic laminate) and advanced packaging technologies, enabling cost and energy efficient, as well as high-performance designs across a wide range of process nodes. The specification was authored to allow many use cases driving significant economies of scale. Care was taken to impose as few constraints as possible and to avoid including required features in the specification that could increase design complexity when disaggregating an existing SoC.
The BoW specification, with an open license making it available to everyone, is already in use in at least 10 companies, including Samsung and NXP, over a dozen different use cases spanning 5, 6, 12, 16, 22 and 65nm process nodes, and covering Chiplet-based products for networking, specialized AI silicon, FPGAs, and processors.
“The semiconductor industry continues to innovate in new and exciting directions with multicore application specific SoCs, custom core architectures, deep learning, optical communications, analog processing techniques, RF interfaces, memory architectures and more. The new challenge is how to integrate all of these disparate innovations, several of which are not practical to produce at cutting- edge process nodes. Today’s announcement from the OCP ODSA, releasing the Bunch of Wires open-source specification for Chiplet interconnect, supplies a new tool toward expanding innovation in the market. This opens the door to a more competitive landscape and diversity in innovation at varying cadences and is fuel or a healthy industry,” said Tom Hackenberg, Principal Analyst, Computing & Software Semiconductor, Memory and Computing Division, Yole Intelligence.
Support from Key Stakeholders
"At Samsung Foundry, we see the BoW specification for Chiplet interconnect from the OCP Foundation as an enabler for the development and advancement of Chiplet designs, standardizing how various Chiplets can talk to each other. This will allow designers to extend to markets beyond just hyperscale, AI and ML and enable heterogeneous integration. We are excited to be working with our SAFE partners to make this capability readily available on the Samsung process technology." Said Sanghune Park, Vice President of Foundry IP team, at Samsung Electronics.
“NXP® strongly supports standards which embrace a broad and inclusive global ecosystem of partners, and ODSA BoW is a great example. We are actively developing a BoW PHY design to validate and demonstrate readiness for future cost-effective and disruptive multi-chip products,” said Mike Leary, vice president of engineering at NXP Semiconductors.
"Keysight Technologies has long designed ASICs and multi-chip packages to enable leading-edge performance in our test and measurement products, and is excited to see the emergence of the BoW specification aimed at low-power, high-bandwidth intra-package data links. BoW's support of both advanced package technologies and organic laminate packages is particularly promising. We are proud to have contributed to this new specification and look forward to its broad acceptance by the semiconductor industry,” said Ken Nishimura, co-Director of ASIC Technology, Keysight Labs.
Blue Cheetah Analog Design
“Blue Cheetah’s BoW-based solutions have been selected by many of our customers to enable their products to participate in a rapidly growing marketplace of Chiplets for disaggregated SoCs. The careful engineering behind the BoW specification has allowed us to realize die-to-die solutions with state-of-the-art power, performance, and area, and we look forward to continuing to participate in ODSA to further advance BoW,” said Elad Alon, CEO of Blue Cheetah.
Ventana Micro Systems
“Ventana has been aggressively pursuing development of Chiplet-based products using BoW in concert with our partners. The BoW PHY spec developed by ODSA brings needed standardization to support the growing trend towards die disaggregation of traditional monolithic silicon into modular composable Chiplets that can use traditional organic packaging or newer advanced forms of packaging,” said Greg Favor, CTO, Ventana.
“DreamBig is developing hyperscale Smart NIC/DPU Chiplet solutions. ODSA BoW is one of the first die-to-die interconnect standards supported on our open platform. BoW enables leading performance-per-Watt-per-packaging-dollar (PPWPPD) and has proven to be versatile designing links between a wide variety of networking, compute, accelerator, memory, and other data center Chiplets across a vast ecosystem of partners,” said Steve Majors, SVP of Engineering at DreamBig Semiconductor.
“d-Matrix is leveraging the ODSA BoW standard to develop a die-die interconnect for it’s Chiplet based AI compute platform targeted at datacenter inference,” said Sid Sheth, Founder, President and CEO at d-Matrix, “The energy efficiency of the high-speed interconnect over organic substrates provided an attractive option to connect Chiplets in a cost-effective fashion.”
“At eTopus we are working with multiple clients utilizing ODSA’s Bunch of Wires standard to connect Chiplets with low power and latency. We are only at the beginning of the adoption curve and see many additional applications for ODSA BoW,” said Harry Chan, CEO of eTopus.