The Open Compute Project’s (OCP) Open Chiplet Economy Project held an educational and informative day-long breakout session on October 15th at the OCP Global Summit, highlighting the latest developments in the silicon and packaging industry, adoption of Chiplets and the next steps within the OCP Community that will impact the industry over the next 12 months.
Chiplets will play an important role enabling diverse silicon systems as we transition from Cloud to AI training and inference compute architectures within the data center, and out to the edge. Open, interoperable and diverse silicon systems are essential to deploying economically viable and dynamic AI Clusters capable of achieving world-leading performance in HPC and AI workloads. The OCP Open Chiplet Economy Project is leading the charge to move the industry from an in-house and mostly closed, large vendor-led ecosystems to open and standardized ecosystems with advancements driven by collaborations between companies.
Key Open Chiplet Economy news shared at the OCP Global Summit covered a potentially industry-changing event with Arm contributing a vendor-neutral specification derived from Arm’s Chiplet System Architecture (CSA), called Foundation Chiplet System Architecture (FCSA).
The theme of the breakout session was the need for full stack system chiplet interoperability, and in case you could not attend, all talks are recorded and the slides can be accessed here.
Topics that were covered include:
- Analyzing HPC and AI workloads for die disaggregation planning
- Roofline analysis and profiling of HPC applications to guide system design
- Proposing Chiplet systems architecture solutions for various market segments
- Splitting the Die: A Modular Approach to Chiplet Design and Verification
- Smashing Memory & I/O Limits: Architectures for the GenAI Era
- Accelerating Chiplet Integration Through ASE VIPack and Arm Total Design Collaboration
- Rearchitecting AI Infrastructure with General-Purpose and Accelerator Chiplets
- Standardized EDA design kits enabling integrated Chiplet design and business workflows
- CDX Innovations in Chiplet Design: From Standardization to System Realization
- Exploring Co-packaged optics solutions with Chiplets
- Delivering on Co-packaged Optics with Chiplets
- Review of Application-specific D2D protocols, Link Layer and Transaction standardizations
- OCE Transaction and Link Layer Specification 1.2
- Universal Die-to-Die Chiplet Interfacing Standards – describing a PHY agnostic link layer
- BoW 2.1 Enhancements (low data rate, IoT, low latency, and power) for New Applications
- Cover Testing, Validation and Prototyping of Chiplet Based Systems
- Accelerating Early-Stage Exploration with Virtual Prototyping for a Flourishing Multi-Vendor Chiplet Economy
- UCIe-Based Chiplet Ecosystem: Interoperable Testbench for Multi-Vendor IP Integration
- Building an Interoperable Chiplet Ecosystem through Golden Die Validation with Pre-Silicon Correlation