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Description:
The pressure on silicon development is intense. The cost of advanced nodes, time to market demands, and need for efficient performance has never been higher. Silicon designers are turning to chiplet technologies to reduce costs, speed time to market, and build workload-accelerated custom silicon. The proliferation of AI is fueling this demand.
But today’s chiplet technologies are single-vendor silos. For an open marketplace of compatible chiplets to develop, silicon designers need the guidance, technologies, and standards to make this happen. How can I properly partition a large design into chiplets, considering security and performance? How do I take a set of chiplets and correctly integrate them into a common substate? How do I validate that my design is compatible and performing to expectation?
This webinar will walk through decisions to consider when partitioning a large design into chiplets, or integrating chiplets into a larger whole. It will outline what to look for at an architecture level – PHY, protocol, and data-link properties – to better integrate chiplets. It will address considerations for different SoC topologies – like coherent SMP, accelerator attach, or IO hub and spoke – that are being implemented today. And it will demonstrate how to address these challenges leveraging widely adopted, well-proven, existing standards, technology ecosystems for solution development, and software.
During the webinar, you’ll learn:
- How to partition monolithic designs into chiplets
- Partition considerations based on popular topologies like coherent SMP, accelerator attach, and IO hub and spoke
- Properties to look for in a system architecture, at a PHY, protocol, and data-link level, to make it easier to integrate and debug chiplets
- The role software plays in configuring device interfaces
- Solutions available in the marketplace today that leverage open, high-performance, widely adopted standards
Who should attend?
Data Center Infrastructure Vendors, Silicon Vendors, Colocation Providers, Cloud and Telecom Service Providers, IT buyers and Decision Makers, and Enterprise CIO and CTO
Speakers:
James Kelly
VP Market Intelligence and Innovation, Open Compute Project Foundation (OCP)
James joined the OCP Foundation staff in 2024 as VP Market Intelligence and Innovation, working with technology leaders in the community and augmenting the foundation’s directional strategy, innovation efforts and marketing. His contributions to the OCP proceed from over two decades of experience in technology research, engineering, product management and marketing.
Xiaoxi He, Ph.D.
Research Director, IDTechEx
Dr. Xiaoxi He is a Research Director at IDTechEx. Since joining in 2014, she has been conducting technology scouting & bench-marking, doing market research & analysis, providing player assessment & evaluation and offering business insights and opinions on emerging technologies. At IDTechEx, she works in Semiconductor technologies. Xiaoxi holds a Ph.D. in Physics from Cavendish Laboratory, Department of Physics at University of Cambridge. She speaks Chinese (Mandarin) and English.
Sridhar Valluru
Director of Product Management, Arm
Sridhar Valluru is Director of Product Management at Arm, where his focus is on Neoverse infrastructure products. Sridhar has extensive experience in the industry working on various silicon product development roles before moving to product management. He has Masters in Electrical Engineering from Univ of Houston and Masters in Business Administration from McCombs School of Business, The Univ of Texas. He also holds 5 patents.