Academia Industry Engagement

Academic and Industry Engagement - Workstream #10

Back to Time Appliances Project's wiki

Goal

The Time Synchronization Industry-Academia workstream (TSIAW) brings together researchers and industry practitioners to discuss and solve challenging problems in time synchronization of connected devices and applications.

Mission Statement

· To promote the advancement of precise time in data center and edge/networked designs and applications

· To get software developer to think differently about how they write software for synchronized applications and to remove 50 years of software hacks and band-aids required to work-around the lack of time synchronization

· Identifying and promoting data to help decision makers on the topic of precise time.

Organization

· Identify and distribute key research areas in time synchronization.

· Organize virtual meetings to bring together researchers and industry practitioners to discuss and demo current challenges and novel solutions.

· Top submission can present at OCP conference or recommended to other conferences.

· Create a central repository for research findings, papers, presentations and best practices related to time synchronization (OCP-TAP wiki for this)

Objective

Bridge the gap between theory and practice

The TSIAW will act as a bridge between academic research and industry needs. By bringing together researchers and practitioners, the workstream will ensure that research efforts address real-world challenges faced by the ever-growing and complex data center and edge communication networks and devices by developing robust, reliable and scalable novel solutions

Synchronization Data for Decision Makers

Research and develop the data required by data center decision makers, on how to use precise time to make data center and edge applications (AI, Databases, Microservices, etc.) or portions of that software run 2x to 1000+x better in performance, power, latency and/or cost when compared to unsynchronized solution.

Develop Time Synchronization Projects

The TSIAW will expose projects for academia that will have impact on data center and edge technologies. When possible, TSIAW will help facilitating the research. When possible, making a community of time synchronization experts available to Academia and Industry to improve applications through time synchronization.

Advance the field of time synchronization

The TSIAW will strive to push the boundaries of time synchronization research by facilitating collaboration between industry and academia. This will involve identifying critical research areas, promoting joint research projects, and disseminating findings and solutions through conferences, workshops, repositories, and publications. (First virtually) (Not focused on crazy precise, more on applications)

Foster a dynamic, vibrant and knowledgeable community of time synchronization experts

The TSIAW will create a platform for communication and collaboration among industry professionals, academics, and researchers working on time synchronization

Project Team

- Lead: Dan Biderman (Intel)

- Lead: Hesham Albakoury (Individual)

Meeting invite

8:00am - 8:30am PST Second Thursday every month: Launch Teams Meeting Link

Recording from Past Calls

Wednesday May 1st 2024 Work Stream Introduction 20 Jan 2022

Projects

	Call For Action	Statement	Introduction Slides	Wiki
#1	Artificial Intelligence / Machine Learning College Project	A Precisely Synchronized Datacenter Would Improve Overall Performance of Distributed Artificial Intelligence and Machine Learning

Software

	Design	Objective
#1	Time Card based PPS measurement	Interface with Time Card driver and export PPS measurement data in a useful format

Potential Future Hardware Solutions

	Core Hardware	Objective
#1	TDC	Small, cheap, and low power use-case
#2	PTM controller	A PCIe based daughter card that can be synchronized with a high stability source (Time Card) over PCIe to scale PPS measurements
#3	UWB	A method for distributing GPS and time to areas where measurements are made, but GPS is not available
#4	DPLL	A discrete design based around a DPLL , removing the need for an FPGA