Keynotes

Prof Onur Mutlu

ETH Zurich

 

Onur Mutlu is a Professor of Computer Science at ETH Zurich and a faculty member at Carnegie Mellon University, where he previously held the Strecker Early Career Professorship. He obtained his PhD in ECE from the UT Austin and held various product / research positions at Microsoft Research, Intel, AMD, VMware, and Google. His various inventions have influenced industry and been deployed in commercial microprocessors and memory/storage systems. Onur received many awards, including IEEE High Performance Computer Architecture Test of Time Award, the IEEE Edward J. McCluskey Technical Achievement Award, ACM SIGARCH Maurice Wilkes Award, and numerous best paper or "Top Pick" paper recognitions. He is an ACM Fellow, IEEE Fellow, and an elected member of the Academy of Europe (Academia Europaea). 

John Wilson

Nvidia

John Wilson has been a member of the Circuits Research Group at NVIDIA Research since 2012. He recently led a team in the design of a 25Gbps Single-Ended Ground Referenced Signaling link, in 16nm FinFET CMOS, enabling TeraByte per-second communication for on-package and off-package channels at 1.17pJ/bit. Currently, he works as a gateway between research/development and productization, while also driving the pathfinding process for future interconnect and data-movement solutions. He received the BS, MS, & Ph.D. degrees in Electrical Engineering from North Carolina State University. His interests include high-speed I/O circuit design, on-chip signaling, signal integrity, advanced packaging, and chip/package co-design. From 2003-2006 he was a Research Professor at NCSU leading projects in advanced packaging, low-power capacitive & inductive coupled transceivers for 3D-ICs, and circuits for on-chip global signaling. From 2006-2012, while with Rambus, Inc. in Chapel Hill, NC, he worked on high-speed I/O circuit design, and methods to mitigate signal & power integrity problems in memory interfaces. He has 72+ publications, 47+ granted patents, and is a Senior Member of the IEEE.    

Dr John Wu

AMD

John Wuu is a Senior Fellow Design Engineer at AMD in Fort Collins, Colorado, specializing in SRAM technology and design, high performance cache design, and chiplet DTCO.  In addition to working across the company to define and deliver SRAM solutions, his recent contributions included the physical definition and technology co-development for AMD’s 3D V-Cache™, the industry’s first 3D stacked high performance processor using the Hybrid Bond technology.  Prior to joining AMD in 2006, he had been with Hewlett-Packard and then Intel, working on large L3 caches for Itanium processors.  He received his Bachelors and Masters degrees from MIT in 1997, and has served as a Technical Program Committee member for the VLSI Symposium since 2016.

Dr Raja Swaminathan

AMD

Dr. Raja Swaminathan is a Senior Fellow at AMD responsible for package architectures and advanced technology strategy and development with ecosystem partners. He was a package architect at Intel for 13 years, moved to Apple to develop their M1x silicon package architectures before moving to AMD to drive their industry leading chiplet architecture integration, including the recently released 3D V-Cache and 2.5D EFB package architectures. He received his Bachelors’ from IIT Madras and PhD from Carnegie Mellon University. He has over 35 US patents in the field, an IEEE Senior Member and he is on the technical advisory board for the Semiconductor research corporation (SRC).
 

Bob Brennan

Intel