All times are in EST.

Start Stop Track Title Speaker(Company)
8:00   Room Opens
8:00am 8:05am Opening Remarks HipChips Program Committee: Dharmesh Jani (Meta)
8:05am 8:30am Keynote Memory Centric Computing Prof. Onur Mutlu (ETH Zurich)
8:30am 8:55am Breakfast
8:55am 9:10am Chiplet Design & Architecure Chiplet-based Waferscale Computing Dr. Rakesh Kumar (UIUC)
9:10am 9:25am Standards and ECO OCP Open Domain Specific Architecture(ODSA): Approach to Creating Open Chiplet Ecosystem under OCP


Bapi Vinnikota (BRCM)

Dharmesh Jani (Meta)

9:25am 9:40am Standards and ECO OCP Open Domain Specific Architecture (ODSA)'s Bunch of Wire (BoW) Interface for Die to Die Applications


Bapi Vinnikota (BRCM)

Elad Alon(BCA)

Jayaprakash B. (Cisco)

9:40am 9:55am Standards and ECO Redefining Computing Architecture Boundaries with Pluggable Chiplets Allan Cantle (Nallasway)
9:55am 10:10am SW for Chiplets HALO: a compiler framework for heterogeneous chiplet architectures with near-zero interconnect latencies

Weiming Zhao (Alibaba)

Weifeng Zhang (Alibaba)

10:10am 10:35am Keynote The Case for a Universal Chiplet Revolution Cliff Young (Google)
10:35am 10:50am Chiplet Design & Architecure HPC/AI system opportunity with integrated photonics chiplets Eduard Roytman (Intel)
10:50am 11:05am Standards and ECO What is the right Die-to-Die Interface? A Comparison Study

Shahab Ardalan

Bapi Vinnikota (BRCM)

Tawfik Arabi (AMD)

Elad Alon (BCA)

11:05am 11:20am Chiplet Design & Architecure Heterogeneous Chiplet-based Architecture for In-Memory Acceleration of DNNs

Gokul Krishnan (ASU)

Kevin Cao (ASU)

11:20am 11:35am Chiplet Design & Architecure Dual-Stripline Configuration for Efficient Signal Routing in the Bunch-of-Wires (BOW) Interface

Shalabh Gupta (IIT Bombay)



SW for Chiplets Chiplet Architecture for Large Scale System Design Dr Ken Chang (Cadence)
11:50am 12:05pm SW for Chiplets Software-defined Design for Systems of Chiplets Duncan Haldane (JTIX)
12:05pm 1:00pm Lunch
1:05pm 1:30pm Keynote Chiplet’s March to the 3D V-Cache™ and Beyond AMD: Dr. John Wuu, Raja Swaminathan
1:30pm 1:45pm Chiplet Design & Architecure Configurable IO Chiplet Architecture Rishi Chugh (Cadence)
1:45pm 2:00pm Chiplet Design & Architecure Hyperscaler use cases and challnges for hetergeneous integration

Ravi Agarwal (Meta)

Dharmesh Jani (Meta)

2:00pm 2:15pm Chiplet Design & Architecure Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits

Sung-Kyu Lim (GATech)

Ravi Agarwal (Meta)

2:15pm 2:30pm Standards and ECO Chiplets and Sustainability Srilatha (Bobbie) Mann (Meta)
2:30pm 3:00pm Break
3:00pm 3:25pm Keynote Chiplets open the world of collaboration Bob Brennan (Intel)
3:25pm 3:40pm Chiplet Design & Architecure Cost-Aware Exploration for Chiplet-Based Architecture with Advanced Packaging Technologies

Tianqi Tang (UCSB)

Yuan Xie (UCSB)

3:40pm 3:55pm Chiplet Design & Architecure Designing and Pathfinding Scale-out Chiplet Based Systems Puneet Gupta (UCLA)
3:55pm 4:10pm Chiplet Design & Architecure Using In-Chip Monitoring and Deep Data Analytics for High Bandwidth Die-to-Die Characterization Nil Sever (Proteon Tec)
4:10pm 4:25pm Chiplet Design & Architecure High-Bandwidth Density, Energy-Efficient, Short-Reach Signaling that Enables Massively Scalable Parallelism John Wilson (NVidia)
4:25pm 4:40pm Chiplet Design & Architecure The Road to Data Center Power Efficiency

Tawfik Arabi (AMD)

Anshuman Mittal (AMD)

4:40pm 5:00pm Closing Remarks HipChips Program Committee: Weifeng Zhang (Alibaba)



Deadline for Submission: April 14th

Submission acceptance: April 28th

Agenda Publication: May 10th

Final Papers presentations due by:  June 3rd

Content review and final feedback: June 8-10th

Workshop date: June 19th