
State Machine - |Apache_TOP|i2c_rsu_j_top_v2:RSU_TEST_INST|ufm_if_top_v2:UFM_IF_TOP_INST|max10_ufm:UFM_INST|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|avmm_read_valid_state
Name avmm_read_valid_state.READ_VALID_IDLE avmm_read_valid_state.READ_VALID_PRE_READING avmm_read_valid_state.READ_VALID_READING 
avmm_read_valid_state.READ_VALID_IDLE 0 0 0 
avmm_read_valid_state.READ_VALID_READING 1 0 1 
avmm_read_valid_state.READ_VALID_PRE_READING 1 1 0 

State Machine - |Apache_TOP|i2c_rsu_j_top_v2:RSU_TEST_INST|ufm_if_top_v2:UFM_IF_TOP_INST|max10_ufm:UFM_INST|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_state
Name read_state.READ_STATE_PULSE_SE read_state.READ_STATE_CLEAR read_state.READ_STATE_FINAL read_state.READ_STATE_READY read_state.READ_STATE_DUMMY read_state.READ_STATE_SETUP read_state.READ_STATE_ADDR read_state.READ_STATE_IDLE 
read_state.READ_STATE_IDLE 0 0 0 0 0 0 0 0 
read_state.READ_STATE_ADDR 0 0 0 0 0 0 1 1 
read_state.READ_STATE_SETUP 0 0 0 0 0 1 0 1 
read_state.READ_STATE_DUMMY 0 0 0 0 1 0 0 1 
read_state.READ_STATE_READY 0 0 0 1 0 0 0 1 
read_state.READ_STATE_FINAL 0 0 1 0 0 0 0 1 
read_state.READ_STATE_CLEAR 0 1 0 0 0 0 0 1 
read_state.READ_STATE_PULSE_SE 1 0 0 0 0 0 0 1 

State Machine - |Apache_TOP|i2c_rsu_j_top_v2:RSU_TEST_INST|ufm_if_top_v2:UFM_IF_TOP_INST|max10_ufm:UFM_INST|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state
Name erase_state.ERASE_STATE_ERROR erase_state.ERASE_STATE_RESET erase_state.ERASE_STATE_WAIT_DONE erase_state.ERASE_STATE_WAIT_BUSY erase_state.ERASE_STATE_ADDR erase_state.ERASE_STATE_IDLE 
erase_state.ERASE_STATE_IDLE 0 0 0 0 0 0 
erase_state.ERASE_STATE_ADDR 0 0 0 0 1 1 
erase_state.ERASE_STATE_WAIT_BUSY 0 0 0 1 0 1 
erase_state.ERASE_STATE_WAIT_DONE 0 0 1 0 0 1 
erase_state.ERASE_STATE_RESET 0 1 0 0 0 1 
erase_state.ERASE_STATE_ERROR 1 0 0 0 0 1 

State Machine - |Apache_TOP|i2c_rsu_j_top_v2:RSU_TEST_INST|ufm_if_top_v2:UFM_IF_TOP_INST|max10_ufm:UFM_INST|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_state
Name write_state.WRITE_STATE_ERROR write_state.WRITE_STATE_RESET write_state.WRITE_STATE_WAIT_DONE write_state.WRITE_STATE_WAIT_BUSY write_state.WRITE_STATE_WRITE write_state.WRITE_STATE_ADDR write_state.WRITE_STATE_IDLE 
write_state.WRITE_STATE_IDLE 0 0 0 0 0 0 0 
write_state.WRITE_STATE_ADDR 0 0 0 0 0 1 1 
write_state.WRITE_STATE_WRITE 0 0 0 0 1 0 1 
write_state.WRITE_STATE_WAIT_BUSY 0 0 0 1 0 0 1 
write_state.WRITE_STATE_WAIT_DONE 0 0 1 0 0 0 1 
write_state.WRITE_STATE_RESET 0 1 0 0 0 0 1 
write_state.WRITE_STATE_ERROR 1 0 0 0 0 0 1 

State Machine - |Apache_TOP|i2c_rsu_j_top_v2:RSU_TEST_INST|ufm_if_top_v2:UFM_IF_TOP_INST|ufm_data_if_v2:UFM_DATA_IF_INST|D_ST
Name D_ST.D_IDLE_ST D_ST.D_WRITE_ST D_ST.D_READ_ST 
D_ST.D_IDLE_ST 0 0 0 
D_ST.D_READ_ST 1 0 1 
D_ST.D_WRITE_ST 1 1 0 

State Machine - |Apache_TOP|i2c_rsu_j_top_v2:RSU_TEST_INST|ufm_if_top_v2:UFM_IF_TOP_INST|ufm_csr_if:UFM_CSR_IF_INST|CSR_ST
Name CSR_ST.CSR_IDLE_ST CSR_ST.CSR_WRITE_ST CSR_ST.CSR_READ_ST 
CSR_ST.CSR_IDLE_ST 0 0 0 
CSR_ST.CSR_READ_ST 1 0 1 
CSR_ST.CSR_WRITE_ST 1 1 0 

State Machine - |Apache_TOP|i2c_rsu_j_top_v2:RSU_TEST_INST|dual_boot_if:DUAL_BOOT_INST|DB_ST
Name DB_ST.DB_IDLE_ST DB_ST.DB_WRITE_ST DB_ST.DB_READ_ST 
DB_ST.DB_IDLE_ST 0 0 0 
DB_ST.DB_READ_ST 1 0 1 
DB_ST.DB_WRITE_ST 1 1 0 

State Machine - |Apache_TOP|i2c_rsu_j_top_v2:RSU_TEST_INST|dual_boot_if:DUAL_BOOT_INST|max10_dual_boot:DUAL_BOOT_INST|altera_dual_boot:dual_boot_0|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|current_state
Name current_state.STATE_CLR_BUSY current_state.STATE_CLR_END current_state.STATE_CLR_WR_INREG current_state.STATE_CLR_RD_INREG current_state.STATE_CLR_RD_APP2 current_state.STATE_CLR_RD_APP1 current_state.STATE_CLR_RD_WD current_state.STATE_CLR current_state.STATE_WRITE_UPDATE current_state.STATE_WRITE current_state.STATE_WRITE_SETUP current_state.STATE_READ_UPDATE current_state.STATE_READ_EXTRA current_state.STATE_READ current_state.STATE_READ_CAPTURE current_state.STATE_READ_DUMMY current_state.STATE_READ_WRITE current_state.STATE_READ_SETUP current_state.STATE_SAME current_state.STATE_INIT 
current_state.STATE_INIT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
current_state.STATE_SAME 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
current_state.STATE_READ_SETUP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
current_state.STATE_READ_WRITE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
current_state.STATE_READ_DUMMY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
current_state.STATE_READ_CAPTURE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
current_state.STATE_READ 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
current_state.STATE_READ_EXTRA 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
current_state.STATE_READ_UPDATE 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
current_state.STATE_WRITE_SETUP 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
current_state.STATE_WRITE 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_WRITE_UPDATE 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_CLR 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_CLR_RD_WD 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_CLR_RD_APP1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_CLR_RD_APP2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_CLR_RD_INREG 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_CLR_WR_INREG 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_CLR_END 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_CLR_BUSY 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |Apache_TOP|i2c_rsu_j_top_v2:RSU_TEST_INST|i2c_rsu_if_v2:I2C_4RSU_INST|I2C_to_rsu:I2C_to_rsu_inst|state_p
Name state_p.010110 state_p.010101 state_p.010100 state_p.010011 state_p.001001 state_p.001000 state_p.000111 state_p.000110 state_p.000101 state_p.000100 state_p.000011 state_p.000010 state_p.000001 state_p.000000 
state_p.000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
state_p.000001 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
state_p.000010 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
state_p.000011 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
state_p.000100 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
state_p.000101 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
state_p.000110 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
state_p.000111 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
state_p.001000 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
state_p.001001 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
state_p.010011 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
state_p.010100 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
state_p.010101 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
state_p.010110 1 0 0 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |Apache_TOP|shift_ctrl_led:shift_ctrl_led_inst|state1
Name state1.data_hd state1.shift state1.start state1.idle 
state1.idle 0 0 0 0 
state1.start 0 0 1 1 
state1.shift 0 1 0 1 
state1.data_hd 1 0 0 1 

State Machine - |Apache_TOP|shift_ctrl_led:shift_ctrl_led_inst|state0
Name state0.data_hd state0.shift state0.start state0.idle 
state0.idle 0 0 0 0 
state0.start 0 0 1 1 
state0.shift 0 1 0 1 
state0.data_hd 1 0 0 1 

State Machine - |Apache_TOP|I2C_to_EMIF:I2C_to_EMIF|state_p
Name state_p.010110 state_p.010101 state_p.010100 state_p.010011 state_p.001001 state_p.001000 state_p.000111 state_p.000110 state_p.000101 state_p.000100 state_p.000011 state_p.000010 state_p.000001 state_p.000000 
state_p.000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
state_p.000001 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
state_p.000010 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
state_p.000011 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
state_p.000100 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
state_p.000101 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
state_p.000110 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
state_p.000111 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
state_p.001000 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
state_p.001001 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
state_p.010011 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
state_p.010100 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
state_p.010101 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
state_p.010110 1 0 0 0 0 0 0 0 0 0 0 0 0 1 
