| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| RSU_TEST_INST|UFM_IF_TOP_INST|UFM_INST|onchip_flash_0|altera_onchip_flash_block |
34 |
2 |
0 |
2 |
36 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|UFM_IF_TOP_INST|UFM_INST|onchip_flash_0|avmm_data_controller|sector_convertor |
3 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|UFM_IF_TOP_INST|UFM_INST|onchip_flash_0|avmm_data_controller|sector_address_write_protection_checker |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|UFM_IF_TOP_INST|UFM_INST|onchip_flash_0|avmm_data_controller|access_address_write_protection_checker |
28 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|UFM_IF_TOP_INST|UFM_INST|onchip_flash_0|avmm_data_controller|address_convertor |
23 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|UFM_IF_TOP_INST|UFM_INST|onchip_flash_0|avmm_data_controller|address_range_checker |
23 |
6 |
0 |
6 |
1 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|UFM_IF_TOP_INST|UFM_INST|onchip_flash_0|avmm_data_controller |
125 |
6 |
3 |
6 |
76 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|UFM_IF_TOP_INST|UFM_INST|onchip_flash_0|avmm_csr_controller |
47 |
4 |
4 |
4 |
64 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|UFM_IF_TOP_INST|UFM_INST|onchip_flash_0 |
92 |
0 |
0 |
0 |
66 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|UFM_IF_TOP_INST|UFM_INST |
92 |
0 |
0 |
0 |
66 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|UFM_IF_TOP_INST|UFM_DATA_IF_INST|ADDR_LD_EDGE_INST |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|UFM_IF_TOP_INST|UFM_DATA_IF_INST |
116 |
5 |
28 |
5 |
91 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|UFM_IF_TOP_INST|UFM_CSR_IF_INST |
90 |
1 |
21 |
1 |
71 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|UFM_IF_TOP_INST |
138 |
0 |
0 |
0 |
66 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|DUAL_BOOT_INST|DUAL_BOOT_INST|dual_boot_0|alt_dual_boot_avmm_comp |
39 |
0 |
28 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|DUAL_BOOT_INST|DUAL_BOOT_INST|dual_boot_0 |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|DUAL_BOOT_INST|DUAL_BOOT_INST |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|DUAL_BOOT_INST |
34 |
6 |
19 |
6 |
9 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|I2C_4RSU_INST|rsu_reg_inst |
101 |
1 |
7 |
1 |
177 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|I2C_4RSU_INST|I2C_to_rsu_inst |
11 |
1 |
0 |
1 |
24 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST|I2C_4RSU_INST |
78 |
0 |
0 |
0 |
168 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| RSU_TEST_INST |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| CLKGEN_INST|APLL_INST|altpll_component|auto_generated |
3 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| CLKGEN_INST|APLL_INST |
2 |
1 |
0 |
1 |
3 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| CLKGEN_INST |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INTERRUPT_CONTROL_INST |
60 |
7 |
2 |
7 |
6 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| RESET_CONTROL_INST|tsen_dly_2 |
11 |
8 |
0 |
8 |
1 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| RESET_CONTROL_INST|tsen_dly_1 |
11 |
8 |
0 |
8 |
1 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| RESET_CONTROL_INST|misc_dly |
11 |
8 |
0 |
8 |
1 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| RESET_CONTROL_INST|phy_dly |
11 |
8 |
0 |
8 |
1 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| RESET_CONTROL_INST|mac_dly |
11 |
8 |
0 |
8 |
1 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| RESET_CONTROL_INST|pll_dly |
11 |
8 |
0 |
8 |
1 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| RESET_CONTROL_INST|bmc_ddr_dly |
11 |
8 |
0 |
8 |
1 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| RESET_CONTROL_INST|bmc_dly |
11 |
8 |
0 |
8 |
1 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| RESET_CONTROL_INST|bmc_pcie_dly |
11 |
8 |
0 |
8 |
1 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| RESET_CONTROL_INST |
51 |
1 |
18 |
1 |
23 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| shift_ctrl_led_inst |
36 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| led_bitstream_ctrl_inst |
51 |
5 |
9 |
5 |
32 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| OUTPUT_CONTROL_INST |
42 |
0 |
20 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_STATUS_INST|psu2_prs_risingedge_latch |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| INPUT_STATUS_INST|psu1_prs_risingedge_latch |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| INPUT_STATUS_INST|psu2_prs_fallingedge_latch |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| INPUT_STATUS_INST|psu1_prs_fallingedge_latch |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| INPUT_STATUS_INST |
59 |
48 |
1 |
48 |
104 |
48 |
48 |
48 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|RST_SW_BTN_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|RST_PCIE_CPU_TO_MB_N_DB_INST |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|RST_PLTRST_N_DB_INST |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_TSEN_NMI_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|MAC_MCUPLL_LOCK_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_HWM_ALERT_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|GNSS_ANT_ON_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|GNSS_ANT_OPEN_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|GNSS_ANT_SHORT_N_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|SFP28_PWR_OC_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|QSFP28_PWR_OC_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|SFP_PWR_OC_GP3_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|SFP_PWR_OC_GP2_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|SFP_PWR_OC_GP1_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_QSFP28_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_SFP_ABS_N0_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_SFP_ABS_N1_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_SFP_LOS_N1_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_SFP_LOS_N0_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_SFP_FLT_N1_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_SFP_FLT_N0_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_CJA_LOL_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_CJA_INTR_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_BITS_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_PHY3_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_PHY1_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_MAC_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|MAC_COREPLL_LOCK_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_SMU_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT1_GNSS_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT0_GNSS_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_USB_BRIDGE_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_TSEN_ALRT_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_HWM_NMI_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_PSU2_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_PSU1_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_FAN5_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_FAN4_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_FAN3_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_FAN2_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_FAN1_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|INT_FAN_CARD_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|SMU_DPLL3_LOCK_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|SMU_DPLL2_LOCK_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|SMU_DPLL1_LOCK_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|SMU_INPUT3_LOS_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|SMU_INPUT2_LOS_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|SMU_INPUT1_LOS_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|SMU_INPUT0_LOS_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST|USB_PWR_OC_N_DB_INST |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| INPUT_DEBOUNCE_INST |
47 |
0 |
0 |
0 |
44 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| clock_gen_inst |
1 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| LPC_to_EMIF |
11 |
0 |
0 |
0 |
30 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
| I2C_to_EMIF |
11 |
1 |
0 |
1 |
24 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| bus_switch |
184 |
24 |
2 |
24 |
145 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |