iic_to_spi

2018.08.14.16:48:58 Datasheet
Overview
  clk_0  iic_to_spi

All Components
   intel_uP_interface_0 intel_uP_interface 1.1
   mm_bridge_0 altera_avalon_mm_bridge 16.1
   uart_gps altera_avalon_uart 16.1
   uart_gps_read_fifo altera_avalon_fifo 16.1
   uart_tod altera_avalon_uart 16.1
   uart_tod_read_fifo altera_avalon_fifo 16.1
Memory Map
i2cslave_to_avlmm_bridge_0
 avalon_master
  intel_uP_interface_0
avalon_slave_0  0x00000000
  uart_gps
s1  0x00000020
  uart_gps_read_fifo
in  0x000000a0
out  0x000000a4
in_csr  0x00000060
  uart_tod
s1  0x00000040
  uart_tod_read_fifo
in  0x000000b0
out  0x000000b4
in_csr  0x00000080

clk_0

clock_source v16.1


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

i2cslave_to_avlmm_bridge_0

altera_i2cslave_to_avlmm_bridge v16.1
clk_0 clk   i2cslave_to_avlmm_bridge_0
  clock
clk_reset  
  reset
avalon_master   intel_uP_interface_0
  avalon_slave_0
avalon_master   uart_tod_read_fifo
  in
avalon_master  
  in_csr
avalon_master  
  out
avalon_master   uart_gps_read_fifo
  in
avalon_master  
  in_csr
avalon_master  
  out
avalon_master   uart_gps
  s1
avalon_master   uart_tod
  s1


Parameters

I2C_SLAVE_ADDRESS 98
BYTE_ADDRESSING 1
ADDRESS_STEALING 0
READ_ONLY 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_uP_interface_0

intel_uP_interface v1.1
i2cslave_to_avlmm_bridge_0 avalon_master   intel_uP_interface_0
  avalon_slave_0
clk_0 clk  
  clock
clk_reset  
  reset_sink


Parameters

DATA_WIDTH 32
T0 2
T1 5
T2 5
T3 5
T4 5
T5 5
T6 10
T7 5
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mm_bridge_0

altera_avalon_mm_bridge v16.1
clk_0 clk   mm_bridge_0
  clk
clk_reset  
  reset
m0   uart_tod_read_fifo
  in
m0  
  in_csr
m0  
  out
m0   uart_gps_read_fifo
  in
m0  
  in_csr
m0  
  out
m0   uart_gps
  s1
m0   uart_tod
  s1


Parameters

DATA_WIDTH 32
SYMBOL_WIDTH 8
ADDRESS_WIDTH 8
SYSINFO_ADDR_WIDTH 8
USE_AUTO_ADDRESS_WIDTH 0
AUTO_ADDRESS_WIDTH 8
HDL_ADDR_WIDTH 8
ADDRESS_UNITS SYMBOLS
BURSTCOUNT_WIDTH 1
MAX_BURST_SIZE 1
MAX_PENDING_RESPONSES 4
LINEWRAPBURSTS 0
PIPELINE_COMMAND 1
PIPELINE_RESPONSE 1
USE_RESPONSE 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

uart_gps

altera_avalon_uart v16.1
i2cslave_to_avlmm_bridge_0 avalon_master   uart_gps
  s1
mm_bridge_0 m0  
  s1
clk_0 clk  
  clk
clk_reset  
  reset


Parameters

baud 115200
dataBits 8
fixedBaud false
parity ODD
simCharStream
simInteractiveInputEnable false
simInteractiveOutputEnable false
simTrueBaud false
stopBits 1
syncRegDepth 2
useCtsRts false
useEopRegister true
useRelativePathForSimFile false
clockRate 50000000
baudError 0.01
parityFisrtChar O
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BAUD 115200
DATA_BITS 8
FIXED_BAUD 0
FREQ 50000000
PARITY 'O'
SIM_CHAR_STREAM ""
SIM_TRUE_BAUD 0
STOP_BITS 1
SYNC_REG_DEPTH 2
USE_CTS_RTS 0
USE_EOP_REGISTER 1

uart_gps_read_fifo

altera_avalon_fifo v16.1
i2cslave_to_avlmm_bridge_0 avalon_master   uart_gps_read_fifo
  in
avalon_master  
  in_csr
avalon_master  
  out
mm_bridge_0 m0  
  in
m0  
  in_csr
m0  
  out
clk_0 clk  
  clk_in
clk_reset  
  reset_in


Parameters

avalonMMAvalonMMDataWidth 32
avalonMMAvalonSTDataWidth 32
bitsPerSymbol 16
channelWidth 8
errorWidth 8
fifoDepth 2048
fifoInputInterfaceOptions AVALONMM_WRITE
fifoOutputInterfaceOptions AVALONMM_READ
showHiddenFeatures false
singleClockMode true
singleResetMode false
symbolsPerBeat 2
useBackpressure false
useIRQ true
usePacket true
useReadControl false
useRegister false
useWriteControl true
deviceFamilyString MAX10FPGA
derived_use_avalonMM_wr_slave true
derived_use_avalonST_sink false
derived_use_avalonMM_rd_slave true
derived_use_avalonST_source false
derived_sink_source_avalonST_width 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

AVALONMM_AVALONMM_DATA_WIDTH 32
AVALONMM_AVALONST_DATA_WIDTH 32
BITS_PER_SYMBOL 16
CHANNEL_WIDTH 8
ERROR_WIDTH 8
FIFO_DEPTH 2048
SINGLE_CLOCK_MODE 1
SYMBOLS_PER_BEAT 2
USE_AVALONMM_READ_SLAVE 1
USE_AVALONMM_WRITE_SLAVE 1
USE_AVALONST_SINK 0
USE_AVALONST_SOURCE 0
USE_BACKPRESSURE 0
USE_IRQ 1
USE_PACKET 1
USE_READ_CONTROL 0
USE_REGISTER 0
USE_WRITE_CONTROL 1

uart_tod

altera_avalon_uart v16.1
i2cslave_to_avlmm_bridge_0 avalon_master   uart_tod
  s1
mm_bridge_0 m0  
  s1
clk_0 clk  
  clk
clk_reset  
  reset


Parameters

baud 115200
dataBits 8
fixedBaud false
parity ODD
simCharStream
simInteractiveInputEnable false
simInteractiveOutputEnable false
simTrueBaud false
stopBits 1
syncRegDepth 2
useCtsRts false
useEopRegister true
useRelativePathForSimFile false
clockRate 50000000
baudError 0.01
parityFisrtChar O
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BAUD 115200
DATA_BITS 8
FIXED_BAUD 0
FREQ 50000000
PARITY 'O'
SIM_CHAR_STREAM ""
SIM_TRUE_BAUD 0
STOP_BITS 1
SYNC_REG_DEPTH 2
USE_CTS_RTS 0
USE_EOP_REGISTER 1

uart_tod_read_fifo

altera_avalon_fifo v16.1
i2cslave_to_avlmm_bridge_0 avalon_master   uart_tod_read_fifo
  in
avalon_master  
  in_csr
avalon_master  
  out
mm_bridge_0 m0  
  in
m0  
  in_csr
m0  
  out
clk_0 clk  
  clk_in
clk_reset  
  reset_in


Parameters

avalonMMAvalonMMDataWidth 32
avalonMMAvalonSTDataWidth 32
bitsPerSymbol 16
channelWidth 8
errorWidth 8
fifoDepth 2048
fifoInputInterfaceOptions AVALONMM_WRITE
fifoOutputInterfaceOptions AVALONMM_READ
showHiddenFeatures false
singleClockMode true
singleResetMode false
symbolsPerBeat 2
useBackpressure false
useIRQ true
usePacket true
useReadControl false
useRegister false
useWriteControl true
deviceFamilyString MAX10FPGA
derived_use_avalonMM_wr_slave true
derived_use_avalonST_sink false
derived_use_avalonMM_rd_slave true
derived_use_avalonST_source false
derived_sink_source_avalonST_width 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

AVALONMM_AVALONMM_DATA_WIDTH 32
AVALONMM_AVALONST_DATA_WIDTH 32
BITS_PER_SYMBOL 16
CHANNEL_WIDTH 8
ERROR_WIDTH 8
FIFO_DEPTH 2048
SINGLE_CLOCK_MODE 1
SYMBOLS_PER_BEAT 2
USE_AVALONMM_READ_SLAVE 1
USE_AVALONMM_WRITE_SLAVE 1
USE_AVALONST_SINK 0
USE_AVALONST_SOURCE 0
USE_BACKPRESSURE 0
USE_IRQ 1
USE_PACKET 1
USE_READ_CONTROL 0
USE_REGISTER 0
USE_WRITE_CONTROL 1
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