Timing Report Min Delay Analysis

SmartTime Version v11.5
Microsemi Corporation - Microsemi Libero Software Release v11.5 (Version 11.5.0.26)
Date: Tue Feb 03 16:43:14 2015


Design: INTEL_RCC_FPGA_X100
Family: SmartFusion
Die: A2F200M3F
Package: 256 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               CLKA_PAD
Period (ns):                4.000
Frequency (MHz):            250.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               CLK_LPC0
Period (ns):                9.500
Frequency (MHz):            105.263
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        6.391
External Hold (ns):         3.481
Min Clock-To-Out (ns):      3.948
Max Clock-To-Out (ns):      10.892

Clock Domain:               INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q
Period (ns):                11.493
Frequency (MHz):            87.009
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        12.880
External Hold (ns):         -0.569
Min Clock-To-Out (ns):      2.607
Max Clock-To-Out (ns):      9.944

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                26.029
Frequency (MHz):            38.419
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        1.281
External Hold (ns):         0.561
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.574
External Hold (ns):         1.448
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                32.320
Frequency (MHz):            30.941
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        8.543
External Hold (ns):         -0.792
Min Clock-To-Out (ns):      2.524
Max Clock-To-Out (ns):      7.834

                            Input to Output
Min Delay (ns):             2.871
Max Delay (ns):             9.746

END SUMMARY
-----------------------------------------------------

Clock Domain CLKA_PAD

Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_CLKA_INBUF/U0/U0:PAD

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain CLK_LPC0

SET Register to Register

Path 1
  From:                        CORELPC_0/CLPCoII/CLPCLOil[11]:CLK
  To:                          CORELPC_0/CLPCoII/CLPCl0L[1]/U1:D
  Delay (ns):                  1.364
  Slack (ns):
  Arrival (ns):                3.527
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        CORELPC_0/CLPCoII/CLPCLOil[11]:CLK
  To:                          CORELPC_0/CLPCoII/CLPCl0L[2]/U1:D
  Delay (ns):                  1.102
  Slack (ns):
  Arrival (ns):                3.265
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        CORELPC_0/CLPCoII/CLPCLOil[10]:CLK
  To:                          CORELPC_0/CLPCoII/CLPCl0L[4]/U1:D
  Delay (ns):                  1.570
  Slack (ns):
  Arrival (ns):                3.762
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        CORELPC_0/CLPCoII/CLPCLOil[11]:CLK
  To:                          CORELPC_0/CLPCoII/CLPCl0L[0]/U1:D
  Delay (ns):                  1.418
  Slack (ns):
  Arrival (ns):                3.581
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        CORELPC_0/CLPCoII/CLPCLOil[10]:CLK
  To:                          CORELPC_0/CLPCoII/CLPCl0L[6]/U1:D
  Delay (ns):                  1.559
  Slack (ns):
  Arrival (ns):                3.751
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: CORELPC_0/CLPCoII/CLPCLOil[11]:CLK
  To: CORELPC_0/CLPCoII/CLPCl0L[1]/U1:D
  data arrival time                              3.527
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK_LPC0
               +     0.000          Clock source
  0.000                        CLK_LPC0 (r)
               +     0.000          net: CLK_LPC0
  0.000                        CLK_LPC0_pad/U0/U0:PAD (r)
               +     0.403          cell: ADLIB:IOPAD_IN
  0.403                        CLK_LPC0_pad/U0/U0:Y (r)
               +     0.000          net: CLK_LPC0_pad/U0/NET1
  0.403                        CLK_LPC0_pad/U0/U1:YIN (r)
               +     0.018          cell: ADLIB:IOIN_IB
  0.421                        CLK_LPC0_pad/U0/U1:Y (r)
               +     1.742          net: CLK_LPC0_c
  2.163                        CORELPC_0/CLPCoII/CLPCLOil[11]:CLK (r)
               +     0.225          cell: ADLIB:DFN1C0
  2.388                        CORELPC_0/CLPCoII/CLPCLOil[11]:Q (r)
               +     0.827          net: CORELPC_0/CLPCoII/CLPCLOil[11]
  3.215                        CORELPC_0/CLPCoII/CLPCl0L[1]/U0:S (r)
               +     0.156          cell: ADLIB:MX2
  3.371                        CORELPC_0/CLPCoII/CLPCl0L[1]/U0:Y (r)
               +     0.156          net: CORELPC_0/CLPCoII/CLPCl0L[1]/Y
  3.527                        CORELPC_0/CLPCoII/CLPCl0L[1]/U1:D (r)
                                    
  3.527                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK_LPC0
               +     0.000          Clock source
  N/C                          CLK_LPC0 (r)
               +     0.000          net: CLK_LPC0
  N/C                          CLK_LPC0_pad/U0/U0:PAD (r)
               +     0.403          cell: ADLIB:IOPAD_IN
  N/C                          CLK_LPC0_pad/U0/U0:Y (r)
               +     0.000          net: CLK_LPC0_pad/U0/NET1
  N/C                          CLK_LPC0_pad/U0/U1:YIN (r)
               +     0.018          cell: ADLIB:IOIN_IB
  N/C                          CLK_LPC0_pad/U0/U1:Y (r)
               +     4.862          net: CLK_LPC0_c
  N/C                          CORELPC_0/CLPCoII/CLPCl0L[1]/U1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          CORELPC_0/CLPCoII/CLPCl0L[1]/U1:D


END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        LPC_LAD[2]
  To:                          CORELPC_0/CLPCoII/CLPCl0L[2]/U1:D
  Delay (ns):                  1.435
  Slack (ns):
  Arrival (ns):                1.435
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          3.481

Path 2
  From:                        LPC_LAD[2]
  To:                          CORELPC_0/CLPCoII/CLPCl0L[6]/U1:D
  Delay (ns):                  1.333
  Slack (ns):
  Arrival (ns):                1.333
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          3.027

Path 3
  From:                        LPC_LAD[0]
  To:                          CORELPC_0/CLPCoII/CLPClLIL[12]/U1:D
  Delay (ns):                  1.745
  Slack (ns):
  Arrival (ns):                1.745
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          2.904

Path 4
  From:                        LPC_LAD[1]
  To:                          CORELPC_0/CLPCoII/CLPCl0L[1]/U1:D
  Delay (ns):                  2.489
  Slack (ns):
  Arrival (ns):                2.489
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          2.879

Path 5
  From:                        LPC_LAD[3]
  To:                          CORELPC_0/CLPCoII/CLPClLIL[15]/U1:D
  Delay (ns):                  2.008
  Slack (ns):
  Arrival (ns):                2.008
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          2.641


Expanded Path 1
  From: LPC_LAD[2]
  To: CORELPC_0/CLPCoII/CLPCl0L[2]/U1:D
  data arrival time                              1.435
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        LPC_LAD[2] (f)
               +     0.000          net: LPC_LAD[2]
  0.000                        LPC_LAD_pad[2]/U0/U0:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_BI
  0.276                        LPC_LAD_pad[2]/U0/U0:Y (f)
               +     0.000          net: LPC_LAD_pad[2]/U0/NET3
  0.276                        LPC_LAD_pad[2]/U0/U1:YIN (f)
               +     0.018          cell: ADLIB:IOBI_IB_OB_EB
  0.294                        LPC_LAD_pad[2]/U0/U1:Y (f)
               +     0.726          net: LPC_LAD_in[2]
  1.020                        CORELPC_0/CLPCoII/CLPCl0L[2]/U0:B (f)
               +     0.268          cell: ADLIB:MX2
  1.288                        CORELPC_0/CLPCoII/CLPCl0L[2]/U0:Y (f)
               +     0.147          net: CORELPC_0/CLPCoII/CLPCl0L[2]/Y
  1.435                        CORELPC_0/CLPCoII/CLPCl0L[2]/U1:D (f)
                                    
  1.435                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK_LPC0
               +     0.000          Clock source
  N/C                          CLK_LPC0 (r)
               +     0.000          net: CLK_LPC0
  N/C                          CLK_LPC0_pad/U0/U0:PAD (r)
               +     0.484          cell: ADLIB:IOPAD_IN
  N/C                          CLK_LPC0_pad/U0/U0:Y (r)
               +     0.000          net: CLK_LPC0_pad/U0/NET1
  N/C                          CLK_LPC0_pad/U0/U1:YIN (r)
               +     0.022          cell: ADLIB:IOIN_IB
  N/C                          CLK_LPC0_pad/U0/U1:Y (r)
               +     4.410          net: CLK_LPC0_c
  N/C                          CORELPC_0/CLPCoII/CLPCl0L[2]/U1:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          CORELPC_0/CLPCoII/CLPCl0L[2]/U1:D


END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        CORELPC_0/CLPCoII/lad_OUt[0]/U1:CLK
  To:                          LPC_LAD[0]
  Delay (ns):                  2.081
  Slack (ns):
  Arrival (ns):                3.948
  Required (ns):
  Clock to Out (ns):           3.948

Path 2
  From:                        CORELPC_0/CLPCoII/lad_OUt[2]/U1:CLK
  To:                          LPC_LAD[2]
  Delay (ns):                  2.043
  Slack (ns):
  Arrival (ns):                4.524
  Required (ns):
  Clock to Out (ns):           4.524

Path 3
  From:                        CORELPC_0/CLPCoII/lad_OUt[3]/U1:CLK
  To:                          LPC_LAD[3]
  Delay (ns):                  2.254
  Slack (ns):
  Arrival (ns):                4.737
  Required (ns):
  Clock to Out (ns):           4.737

Path 4
  From:                        CORELPC_0/CLPCoII/Lad_OEn/U1:CLK
  To:                          LPC_LAD[0]
  Delay (ns):                  2.584
  Slack (ns):
  Arrival (ns):                5.164
  Required (ns):
  Clock to Out (ns):           5.164

Path 5
  From:                        CORELPC_0/CLPCoII/Lad_OEn/U1:CLK
  To:                          LPC_LAD[3]
  Delay (ns):                  2.584
  Slack (ns):
  Arrival (ns):                5.164
  Required (ns):
  Clock to Out (ns):           5.164


Expanded Path 1
  From: CORELPC_0/CLPCoII/lad_OUt[0]/U1:CLK
  To: LPC_LAD[0]
  data arrival time                              3.948
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK_LPC0
               +     0.000          Clock source
  0.000                        CLK_LPC0 (r)
               +     0.000          net: CLK_LPC0
  0.000                        CLK_LPC0_pad/U0/U0:PAD (r)
               +     0.403          cell: ADLIB:IOPAD_IN
  0.403                        CLK_LPC0_pad/U0/U0:Y (r)
               +     0.000          net: CLK_LPC0_pad/U0/NET1
  0.403                        CLK_LPC0_pad/U0/U1:YIN (r)
               +     0.018          cell: ADLIB:IOIN_IB
  0.421                        CLK_LPC0_pad/U0/U1:Y (r)
               +     1.446          net: CLK_LPC0_c
  1.867                        CORELPC_0/CLPCoII/lad_OUt[0]/U1:CLK (r)
               +     0.225          cell: ADLIB:DFN1P0
  2.092                        CORELPC_0/CLPCoII/lad_OUt[0]/U1:Q (r)
               +     0.515          net: CORELPC_0_LAD_OUT[0]
  2.607                        LPC_LAD_pad[0]/U0/U1:D (r)
               +     0.256          cell: ADLIB:IOBI_IB_OB_EB
  2.863                        LPC_LAD_pad[0]/U0/U1:DOUT (r)
               +     0.000          net: LPC_LAD_pad[0]/U0/NET1
  2.863                        LPC_LAD_pad[0]/U0/U0:D (r)
               +     1.085          cell: ADLIB:IOPAD_BI
  3.948                        LPC_LAD_pad[0]/U0/U0:PAD (r)
               +     0.000          net: LPC_LAD[0]
  3.948                        LPC_LAD[0] (r)
                                    
  3.948                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK_LPC0
               +     0.000          Clock source
  N/C                          CLK_LPC0 (r)
                                    
  N/C                          LPC_LAD[0] (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

Path 1
  From:                        PLTRST_N
  To:                          CORELPC_0/CLPCoII/CLPCl0L[1]/U1:CLR
  Delay (ns):                  3.665
  Slack (ns):
  Arrival (ns):                3.665
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       1.703

Path 2
  From:                        PLTRST_N
  To:                          CORELPC_0/CLPCoII/CLPCl0L[7]/U1:CLR
  Delay (ns):                  3.247
  Slack (ns):
  Arrival (ns):                3.247
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       1.113

Path 3
  From:                        PLTRST_N
  To:                          CORELPC_0/CLPCoII/CLPCl0L[6]/U1:CLR
  Delay (ns):                  3.248
  Slack (ns):
  Arrival (ns):                3.248
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       1.112

Path 4
  From:                        PLTRST_N
  To:                          CORELPC_0/CLPCoII/CLPClLIL[12]/U1:CLR
  Delay (ns):                  3.607
  Slack (ns):
  Arrival (ns):                3.607
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       1.042

Path 5
  From:                        PLTRST_N
  To:                          CORELPC_0/CLPCoII/CLPCl0L[2]/U1:CLR
  Delay (ns):                  3.951
  Slack (ns):
  Arrival (ns):                3.951
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       0.965


Expanded Path 1
  From: PLTRST_N
  To: CORELPC_0/CLPCoII/CLPCl0L[1]/U1:CLR
  data arrival time                              3.665
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        PLTRST_N (r)
               +     0.000          net: PLTRST_N
  0.000                        PLTRST_N_pad/U0/U0:PAD (r)
               +     0.403          cell: ADLIB:IOPAD_IN
  0.403                        PLTRST_N_pad/U0/U0:Y (r)
               +     0.000          net: PLTRST_N_pad/U0/NET1
  0.403                        PLTRST_N_pad/U0/U1:YIN (r)
               +     0.018          cell: ADLIB:IOIN_IB
  0.421                        PLTRST_N_pad/U0/U1:Y (r)
               +     2.401          net: PLTRST_N_c
  2.822                        PLTRST_N_pad_RNIARJC_0:A (r)
               +     0.199          cell: ADLIB:BUFF
  3.021                        PLTRST_N_pad_RNIARJC_0:Y (r)
               +     0.644          net: PLTRST_N_c_0
  3.665                        CORELPC_0/CLPCoII/CLPCl0L[1]/U1:CLR (r)
                                    
  3.665                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK_LPC0
               +     0.000          Clock source
  N/C                          CLK_LPC0 (r)
               +     0.000          net: CLK_LPC0
  N/C                          CLK_LPC0_pad/U0/U0:PAD (r)
               +     0.484          cell: ADLIB:IOPAD_IN
  N/C                          CLK_LPC0_pad/U0/U0:Y (r)
               +     0.000          net: CLK_LPC0_pad/U0/NET1
  N/C                          CLK_LPC0_pad/U0/U1:YIN (r)
               +     0.022          cell: ADLIB:IOIN_IB
  N/C                          CLK_LPC0_pad/U0/U1:Y (r)
               +     4.862          net: CLK_LPC0_c
  N/C                          CORELPC_0/CLPCoII/CLPCl0L[1]/U1:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  N/C                          CORELPC_0/CLPCoII/CLPCl0L[1]/U1:CLR


END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q

SET Register to Register

Path 1
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[2]:CLK
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[1]:D
  Delay (ns):                  0.832
  Slack (ns):
  Arrival (ns):                1.742
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[3]:CLK
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[2]:D
  Delay (ns):                  0.870
  Slack (ns):
  Arrival (ns):                1.127
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/timer_0:CLK
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[10]:D
  Delay (ns):                  1.197
  Slack (ns):
  Arrival (ns):                2.177
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/timer:CLK
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[6]:D
  Delay (ns):                  1.408
  Slack (ns):
  Arrival (ns):                2.388
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/timer:CLK
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/ddr_vcca_pwrok:D
  Delay (ns):                  1.284
  Slack (ns):
  Arrival (ns):                2.264
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[2]:CLK
  To: INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[1]:D
  data arrival time                              1.742
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q
               +     0.000          Clock source
  0.000                        INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q (r)
               +     0.910          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]
  0.910                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[2]:CLK (r)
               +     0.225          cell: ADLIB:DFN1C0
  1.135                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[2]:Q (r)
               +     0.236          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[2]
  1.371                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state_RNO[1]:A (r)
               +     0.222          cell: ADLIB:AO1
  1.593                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state_RNO[1]:Y (r)
               +     0.149          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state_ns[15]
  1.742                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[1]:D (r)
                                    
  1.742                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q (r)
               +     2.022          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[1]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[1]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        DISABLE_10G
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/v3p3_10g_en:E
  Delay (ns):                  1.494
  Slack (ns):
  Arrival (ns):                1.494
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -0.569

Path 2
  From:                        DISABLE_10G
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/v1p2_10g_en:E
  Delay (ns):                  1.716
  Slack (ns):
  Arrival (ns):                1.716
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -0.610

Path 3
  From:                        IO_22_PADIN
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[6]:D
  Delay (ns):                  2.826
  Slack (ns):
  Arrival (ns):                2.826
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -0.669

Path 4
  From:                        PM_V1P0_PWRGD
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[10]:D
  Delay (ns):                  2.880
  Slack (ns):
  Arrival (ns):                2.880
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -0.849

Path 5
  From:                        PM_V1P2_PWRGD
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[9]:D
  Delay (ns):                  3.129
  Slack (ns):
  Arrival (ns):                3.129
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -0.894


Expanded Path 1
  From: DISABLE_10G
  To: INTEL_RCC_FPGA_0/rcc_pwr_inst/v3p3_10g_en:E
  data arrival time                              1.494
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        DISABLE_10G (f)
               +     0.000          net: DISABLE_10G
  0.000                        DISABLE_10G_pad/U0/U0:PAD (f)
               +     0.292          cell: ADLIB:IOPAD_IN
  0.292                        DISABLE_10G_pad/U0/U0:Y (f)
               +     0.000          net: DISABLE_10G_pad/U0/NET1
  0.292                        DISABLE_10G_pad/U0/U1:YIN (f)
               +     0.018          cell: ADLIB:IOIN_IB
  0.310                        DISABLE_10G_pad/U0/U1:Y (f)
               +     0.871          net: DISABLE_10G_c
  1.181                        INTEL_RCC_FPGA_0/rcc_pwr_inst/v3p3_10g_en_RNO:A (f)
               +     0.158          cell: ADLIB:AO1
  1.339                        INTEL_RCC_FPGA_0/rcc_pwr_inst/v3p3_10g_en_RNO:Y (f)
               +     0.155          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/un1_pm_state_27
  1.494                        INTEL_RCC_FPGA_0/rcc_pwr_inst/v3p3_10g_en:E (f)
                                    
  1.494                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q (r)
               +     0.925          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/v3p3_10g_en:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1E0C0
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/v3p3_10g_en:E


END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/v1p35_en:CLK
  To:                          PM_V1P8_EN
  Delay (ns):                  2.350
  Slack (ns):
  Arrival (ns):                2.607
  Required (ns):
  Clock to Out (ns):           2.607

Path 2
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/v12_pcie_en:CLK
  To:                          PM_V12_PCIE_EN
  Delay (ns):                  2.121
  Slack (ns):
  Arrival (ns):                2.645
  Required (ns):
  Clock to Out (ns):           2.645

Path 3
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/v12_pcie_en:CLK
  To:                          PM_V1P0_EN
  Delay (ns):                  2.351
  Slack (ns):
  Arrival (ns):                2.875
  Required (ns):
  Clock to Out (ns):           2.875

Path 4
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/v1p35_en:CLK
  To:                          PM_V1P35_EN
  Delay (ns):                  2.652
  Slack (ns):
  Arrival (ns):                2.909
  Required (ns):
  Clock to Out (ns):           2.909

Path 5
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/v1p1_en:CLK
  To:                          PM_V1P1_EN
  Delay (ns):                  2.663
  Slack (ns):
  Arrival (ns):                2.920
  Required (ns):
  Clock to Out (ns):           2.920


Expanded Path 1
  From: INTEL_RCC_FPGA_0/rcc_pwr_inst/v1p35_en:CLK
  To: PM_V1P8_EN
  data arrival time                              2.607
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q
               +     0.000          Clock source
  0.000                        INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q (r)
               +     0.257          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]
  0.257                        INTEL_RCC_FPGA_0/rcc_pwr_inst/v1p35_en:CLK (r)
               +     0.225          cell: ADLIB:DFN1E0C0
  0.482                        INTEL_RCC_FPGA_0/rcc_pwr_inst/v1p35_en:Q (r)
               +     0.730          net: PM_V1P8_EN_c_c
  1.212                        PM_V1P8_EN_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  1.491                        PM_V1P8_EN_pad/U0/U1:DOUT (r)
               +     0.000          net: PM_V1P8_EN_pad/U0/NET1
  1.491                        PM_V1P8_EN_pad/U0/U0:D (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  2.607                        PM_V1P8_EN_pad/U0/U0:PAD (r)
               +     0.000          net: PM_V1P8_EN
  2.607                        PM_V1P8_EN (r)
                                    
  2.607                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q (r)
                                    
  N/C                          PM_V1P8_EN (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

Path 1
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[0]:CLR
  Delay (ns):                  0.820
  Slack (ns):
  Arrival (ns):                0.820
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       1.426

Path 2
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[7]:CLR
  Delay (ns):                  0.820
  Slack (ns):
  Arrival (ns):                0.820
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       1.426

Path 3
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[1]:CLR
  Delay (ns):                  0.820
  Slack (ns):
  Arrival (ns):                0.820
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       1.426

Path 4
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[5]:CLR
  Delay (ns):                  0.820
  Slack (ns):
  Arrival (ns):                0.820
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       1.426

Path 5
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[9]:CLR
  Delay (ns):                  0.811
  Slack (ns):
  Arrival (ns):                0.811
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       1.424


Expanded Path 1
  From: FPGA_RESET_N
  To: INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[0]:CLR
  data arrival time                              0.820
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        FPGA_RESET_N (r)
               +     0.000          net: FPGA_RESET_N
  0.000                        FPGA_RESET_N_pad/U0/U0:PAD (r)
               +     0.403          cell: ADLIB:IOPAD_IN
  0.403                        FPGA_RESET_N_pad/U0/U0:Y (r)
               +     0.000          net: FPGA_RESET_N_pad/U0/NET1
  0.403                        FPGA_RESET_N_pad/U0/U1:A (r)
               +     0.148          cell: ADLIB:CLKSRC
  0.551                        FPGA_RESET_N_pad/U0/U1:Y (r)
               +     0.269          net: FPGA_RESET_N_c
  0.820                        INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[0]:CLR (r)
                                    
  0.820                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q (r)
               +     2.246          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[0]:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1C0
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[0]:CLR


END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[31]
  Delay (ns):                  3.577
  Slack (ns):
  Arrival (ns):                3.577
  Required (ns):
  Hold (ns):                   1.376

Path 2
  From:                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[21]
  Delay (ns):                  3.858
  Slack (ns):
  Arrival (ns):                3.858
  Required (ns):
  Hold (ns):                   1.396

Path 3
  From:                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[24]
  Delay (ns):                  3.873
  Slack (ns):
  Arrival (ns):                3.873
  Required (ns):
  Hold (ns):                   1.394

Path 4
  From:                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[30]
  Delay (ns):                  3.905
  Slack (ns):
  Arrival (ns):                3.905
  Required (ns):
  Hold (ns):                   1.381

Path 5
  From:                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[17]
  Delay (ns):                  3.946
  Slack (ns):
  Arrival (ns):                3.946
  Required (ns):
  Hold (ns):                   1.395


Expanded Path 1
  From: INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[31]
  data arrival time                              3.577
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     1.770          cell: ADLIB:MSS_APB_IP
  1.770                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[12] (f)
               +     0.078          net: INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/MSSPADDR[12]INT_NET
  1.848                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_34:PIN1INT (f)
               +     0.042          cell: ADLIB:MSS_IF
  1.890                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_34:PIN1 (f)
               +     0.656          net: INTEL_RCC_FPGA_X100_MSS_0_MSS_MASTER_APB_0_PADDR[12]
  2.546                        CoreAPB3_0/CAPB3OOl1/m62:S (f)
               +     0.171          cell: ADLIB:MX2
  2.717                        CoreAPB3_0/CAPB3OOl1/m62:Y (f)
               +     0.607          net: INTEL_RCC_FPGA_X100_MSS_0_MSS_MASTER_APB_0_PRDATA[31]
  3.324                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_58:PIN5 (f)
               +     0.045          cell: ADLIB:MSS_IF
  3.369                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_58:PIN5INT (f)
               +     0.208          net: INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/MSSPRDATA[31]INT_NET
  3.577                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[31] (f)
                                    
  3.577                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     1.376          Library hold time: ADLIB:MSS_APB_IP
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[31]


END SET Register to Register

----------------------------------------------------

SET External Hold

No Path

END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        GPIO_24_IN
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[24]
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   0.837
  External Hold (ns):          0.561

Path 2
  From:                        GPIO_28_IN
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[28]
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   0.759
  External Hold (ns):          0.483

Path 3
  From:                        GPIO_27_IN
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[27]
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   0.679
  External Hold (ns):          0.403

Path 4
  From:                        GPIO_26_IN
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[26]
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   0.671
  External Hold (ns):          0.395

Path 5
  From:                        GPIO_25_IN
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[25]
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   0.613
  External Hold (ns):          0.337


Expanded Path 1
  From: GPIO_24_IN
  To: INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[24]
  data arrival time                              0.276
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        GPIO_24_IN (f)
               +     0.000          net: GPIO_24_IN
  0.000                        INTEL_RCC_FPGA_X100_MSS_0/MSS_GPIO_0_GPIO_24_IN:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        INTEL_RCC_FPGA_X100_MSS_0/MSS_GPIO_0_GPIO_24_IN:Y (f)
               +     0.000          net: INTEL_RCC_FPGA_X100_MSS_0/MSS_GPIO_0_GPIO_24_IN_Y
  0.276                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[24] (f)
                                    
  0.276                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               +     0.837          Library hold time: ADLIB:MSS_APB_IP
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[24]


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        MSS_RESET_N
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.276
  Slack (ns):
  Arrival (ns):                0.276
  Required (ns):
  Hold (ns):                   1.354
  External Hold (ns):          1.448


Expanded Path 1
  From: MSS_RESET_N
  To: INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data arrival time                              0.276
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (f)
               +     0.000          net: MSS_RESET_N
  0.000                        INTEL_RCC_FPGA_X100_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        INTEL_RCC_FPGA_X100_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (f)
               +     0.000          net: INTEL_RCC_FPGA_X100_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.276                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (f)
                                    
  0.276                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.370          net: INTEL_RCC_FPGA_X100_MSS_0/GLA0
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               +     1.354          Library hold time: ADLIB:MSS_APB_IP
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Hold

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

No Path

END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        CoreGPIO_0/CGPIOI1[3]:CLK
  To:                          CoreGPIO_0/CGPIOOOL[3]:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.707
  Required (ns):
  Hold (ns):                   0.000

Path 2
  From:                        INTEL_RCC_FPGA_0/rcc_spi_inst/sreg[6]:CLK
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/reg_addr[7]:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.725
  Required (ns):
  Hold (ns):                   0.000

Path 3
  From:                        INTEL_RCC_FPGA_0/rcc_spi_inst/sreg[4]:CLK
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/reg_addr[5]:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.725
  Required (ns):
  Hold (ns):                   0.000

Path 4
  From:                        INTEL_RCC_FPGA_0/rcc_spi_inst/soc_fpga_data_in_del1:CLK
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/soc_fpga_data_in_del2:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.712
  Required (ns):
  Hold (ns):                   0.000

Path 5
  From:                        CoreGPIO_0/CGPIOI1[0]:CLK
  To:                          CoreGPIO_0/CGPIOOOL[0]:D
  Delay (ns):                  0.397
  Slack (ns):
  Arrival (ns):                0.709
  Required (ns):
  Hold (ns):                   0.000


Expanded Path 1
  From: CoreGPIO_0/CGPIOI1[3]:CLK
  To: CoreGPIO_0/CGPIOOOL[3]:D
  data arrival time                              0.707
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.310          net: FAB_CLK
  0.310                        CoreGPIO_0/CGPIOI1[3]:CLK (r)
               +     0.248          cell: ADLIB:DFN1C0
  0.558                        CoreGPIO_0/CGPIOI1[3]:Q (r)
               +     0.149          net: CoreGPIO_0/CGPIOI1[3]
  0.707                        CoreGPIO_0/CGPIOOOL[3]:D (r)
                                    
  0.707                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.354          net: FAB_CLK
  N/C                          CoreGPIO_0/CGPIOOOL[3]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          CoreGPIO_0/CGPIOOOL[3]:D


END SET Register to Register

----------------------------------------------------

SET External Hold

Path 1
  From:                        PMU_SLP_S3_N
  To:                          CoreGPIO_0/CGPIOI1[1]:D
  Delay (ns):                  1.225
  Slack (ns):
  Arrival (ns):                1.225
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -0.792

Path 2
  From:                        FPGA_JMPR1
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/spi_mux:D
  Delay (ns):                  1.457
  Slack (ns):
  Arrival (ns):                1.457
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -1.079

Path 3
  From:                        IO_16_PADIN
  To:                          CoreGPIO_0/CGPIOI1[2]:D
  Delay (ns):                  1.516
  Slack (ns):
  Arrival (ns):                1.516
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -1.140

Path 4
  From:                        IO_20_PADIN
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/soc_fpga_clk_del1:D
  Delay (ns):                  1.599
  Slack (ns):
  Arrival (ns):                1.599
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -1.220

Path 5
  From:                        IO_22_PADIN
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/thermtrip_n_1:D
  Delay (ns):                  1.824
  Slack (ns):
  Arrival (ns):                1.824
  Required (ns):
  Hold (ns):                   0.000
  External Hold (ns):          -1.473


Expanded Path 1
  From: PMU_SLP_S3_N
  To: CoreGPIO_0/CGPIOI1[1]:D
  data arrival time                              1.225
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        PMU_SLP_S3_N (f)
               +     0.000          net: PMU_SLP_S3_N
  0.000                        PMU_SLP_S3_N_pad/U0/U0:PAD (f)
               +     0.276          cell: ADLIB:IOPAD_IN
  0.276                        PMU_SLP_S3_N_pad/U0/U0:Y (f)
               +     0.000          net: PMU_SLP_S3_N_pad/U0/NET1
  0.276                        PMU_SLP_S3_N_pad/U0/U1:YIN (f)
               +     0.018          cell: ADLIB:IOIN_IB
  0.294                        PMU_SLP_S3_N_pad/U0/U1:Y (f)
               +     0.931          net: PMU_SLP_S3_N_c
  1.225                        CoreGPIO_0/CGPIOI1[1]:D (f)
                                    
  1.225                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.433          net: FAB_CLK
  N/C                          CoreGPIO_0/CGPIOI1[1]:CLK (r)
               +     0.000          Library hold time: ADLIB:DFN1C0
  N/C                          CoreGPIO_0/CGPIOI1[1]:D


END SET External Hold

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        INTEL_RCC_FPGA_0/rcc_spi_inst/spi_mux:CLK
  To:                          SPI_CS_SELECT
  Delay (ns):                  2.210
  Slack (ns):
  Arrival (ns):                2.524
  Required (ns):
  Clock to Out (ns):           2.524

Path 2
  From:                        INTEL_RCC_FPGA_0/rcc_spi_inst/serial_data_out:CLK
  To:                          GPIO_CPU_SUS2
  Delay (ns):                  2.406
  Slack (ns):
  Arrival (ns):                2.734
  Required (ns):
  Clock to Out (ns):           2.734

Path 3
  From:                        CoreGPIO_1/CGPIOo0[1]:CLK
  To:                          CPU_PWRBTN_N
  Delay (ns):                  3.734
  Slack (ns):
  Arrival (ns):                4.057
  Required (ns):
  Clock to Out (ns):           4.057


Expanded Path 1
  From: INTEL_RCC_FPGA_0/rcc_spi_inst/spi_mux:CLK
  To: SPI_CS_SELECT
  data arrival time                              2.524
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.314          net: FAB_CLK
  0.314                        INTEL_RCC_FPGA_0/rcc_spi_inst/spi_mux:CLK (r)
               +     0.248          cell: ADLIB:DFN1E0C0
  0.562                        INTEL_RCC_FPGA_0/rcc_spi_inst/spi_mux:Q (r)
               +     0.567          net: INTEL_RCC_FPGA_0_rcc_spi_inst_spi_mux
  1.129                        SPI_CS_SELECT_pad/U0/U1:D (r)
               +     0.279          cell: ADLIB:IOTRI_OB_EB
  1.408                        SPI_CS_SELECT_pad/U0/U1:DOUT (r)
               +     0.000          net: SPI_CS_SELECT_pad/U0/NET1
  1.408                        SPI_CS_SELECT_pad/U0/U0:D (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  2.524                        SPI_CS_SELECT_pad/U0/U0:PAD (r)
               +     0.000          net: SPI_CS_SELECT_0
  2.524                        SPI_CS_SELECT (r)
                                    
  2.524                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
                                    
  N/C                          SPI_CS_SELECT (r)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Removal

Path 1
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/serial_data_out:PRE
  Delay (ns):                  0.833
  Slack (ns):
  Arrival (ns):                0.833
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       -0.438

Path 2
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/reg_addr[7]:CLR
  Delay (ns):                  0.833
  Slack (ns):
  Arrival (ns):                0.833
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       -0.438

Path 3
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/reg_pwr_cycle:CLR
  Delay (ns):                  0.833
  Slack (ns):
  Arrival (ns):                0.833
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       -0.438

Path 4
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/reg_addr[4]:CLR
  Delay (ns):                  0.833
  Slack (ns):
  Arrival (ns):                0.833
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       -0.438

Path 5
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/reg_addr[2]:CLR
  Delay (ns):                  0.833
  Slack (ns):
  Arrival (ns):                0.833
  Required (ns):
  Removal (ns):                0.000
  External Removal (ns):       -0.438


Expanded Path 1
  From: FPGA_RESET_N
  To: INTEL_RCC_FPGA_0/rcc_spi_inst/serial_data_out:PRE
  data arrival time                              0.833
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        FPGA_RESET_N (r)
               +     0.000          net: FPGA_RESET_N
  0.000                        FPGA_RESET_N_pad/U0/U0:PAD (r)
               +     0.403          cell: ADLIB:IOPAD_IN
  0.403                        FPGA_RESET_N_pad/U0/U0:Y (r)
               +     0.000          net: FPGA_RESET_N_pad/U0/NET1
  0.403                        FPGA_RESET_N_pad/U0/U1:A (r)
               +     0.148          cell: ADLIB:CLKSRC
  0.551                        FPGA_RESET_N_pad/U0/U1:Y (r)
               +     0.282          net: FPGA_RESET_N_c
  0.833                        INTEL_RCC_FPGA_0/rcc_spi_inst/serial_data_out:PRE (r)
                                    
  0.833                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.395          net: FAB_CLK
  N/C                          INTEL_RCC_FPGA_0/rcc_spi_inst/serial_data_out:CLK (r)
               +     0.000          Library removal time: ADLIB:DFN1E0P0
  N/C                          INTEL_RCC_FPGA_0/rcc_spi_inst/serial_data_out:PRE


END SET External Removal

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

Path 1
  From:                        PM_V3P3_PWRGD
  To:                          CPU_PWRBTN_N
  Delay (ns):                  2.871
  Slack (ns):
  Arrival (ns):                2.871
  Required (ns):

Path 2
  From:                        PLTRST_N
  To:                          PHY_RST_N
  Delay (ns):                  3.113
  Slack (ns):
  Arrival (ns):                3.113
  Required (ns):

Path 3
  From:                        PM_V3P3_PWRGD
  To:                          SMB_GBE_CPU_CLK
  Delay (ns):                  3.352
  Slack (ns):
  Arrival (ns):                3.352
  Required (ns):

Path 4
  From:                        RST_XDP_N
  To:                          CPU_RSTBTN_N
  Delay (ns):                  3.415
  Slack (ns):
  Arrival (ns):                3.415
  Required (ns):

Path 5
  From:                        PM_V3P3_PWRGD
  To:                          SMB_GBE_CPU_DATA
  Delay (ns):                  3.556
  Slack (ns):
  Arrival (ns):                3.556
  Required (ns):


Expanded Path 1
  From: PM_V3P3_PWRGD
  To: CPU_PWRBTN_N
  data arrival time                              2.871
  data required time                         -   N/C
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        PM_V3P3_PWRGD (r)
               +     0.000          net: PM_V3P3_PWRGD
  0.000                        PM_V3P3_PWRGD_pad/U0/U0:PAD (r)
               +     0.403          cell: ADLIB:IOPAD_IN
  0.403                        PM_V3P3_PWRGD_pad/U0/U0:Y (r)
               +     0.000          net: PM_V3P3_PWRGD_pad/U0/NET1
  0.403                        PM_V3P3_PWRGD_pad/U0/U1:YIN (r)
               +     0.018          cell: ADLIB:IOIN_IB
  0.421                        PM_V3P3_PWRGD_pad/U0/U1:Y (r)
               +     1.151          net: PM_V3P3_PWRGD_c
  1.572                        CPU_PWRBTN_N_pad/U0/U1:E (r)
               +     0.183          cell: ADLIB:IOTRI_OB_EB
  1.755                        CPU_PWRBTN_N_pad/U0/U1:EOUT (r)
               +     0.000          net: CPU_PWRBTN_N_pad/U0/NET2
  1.755                        CPU_PWRBTN_N_pad/U0/U0:E (r)
               +     1.116          cell: ADLIB:IOPAD_TRI
  2.871                        CPU_PWRBTN_N_pad/U0/U0:PAD (r)
               +     0.000          net: CPU_PWRBTN_N_0
  2.871                        CPU_PWRBTN_N (r)
                                    
  2.871                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          PM_V3P3_PWRGD (r)
                                    
  N/C                          CPU_PWRBTN_N (r)
                                    
  N/C                          data required time


END SET Input to Output

----------------------------------------------------

Path set User Sets

