Timing Report Max Delay Analysis

SmartTime Version v11.5
Microsemi Corporation - Microsemi Libero Software Release v11.5 (Version 11.5.0.26)
Date: Tue Feb 03 16:43:12 2015


Design: INTEL_RCC_FPGA_X100
Family: SmartFusion
Die: A2F200M3F
Package: 256 FBGA
Temperature: COM
Voltage: COM
Speed Grade: -1
Design State: Post-Layout
Data source: Silicon verified
Min Operating Condition: BEST
Max Operating Condition: WORST
Using Enhanced Min Delay Analysis
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               CLKA_PAD
Period (ns):                4.000
Frequency (MHz):            250.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               CLK_LPC0
Period (ns):                9.500
Frequency (MHz):            105.263
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        6.391
External Hold (ns):         3.481
Min Clock-To-Out (ns):      3.948
Max Clock-To-Out (ns):      10.892

Clock Domain:               INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q
Period (ns):                11.493
Frequency (MHz):            87.009
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        12.880
External Hold (ns):         -0.569
Min Clock-To-Out (ns):      2.607
Max Clock-To-Out (ns):      9.944

Clock Domain:               mss_aclk
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_fabric_interface_clock
Period (ns):                26.029
Frequency (MHz):            38.419
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        N/A
External Hold (ns):         N/A
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_pclk1
Period (ns):                N/A
Frequency (MHz):            N/A
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        1.281
External Hold (ns):         0.561
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_gla0
Period (ns):                10.000
Frequency (MHz):            100.000
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        -1.574
External Hold (ns):         1.448
Min Clock-To-Out (ns):      N/A
Max Clock-To-Out (ns):      N/A

Clock Domain:               mss_ccc_glb
Period (ns):                32.320
Frequency (MHz):            30.941
Required Period (ns):       N/A
Required Frequency (MHz):   N/A
External Setup (ns):        8.543
External Hold (ns):         -0.792
Min Clock-To-Out (ns):      2.524
Max Clock-To-Out (ns):      7.834

                            Input to Output
Min Delay (ns):             2.871
Max Delay (ns):             9.746

END SUMMARY
-----------------------------------------------------

Clock Domain CLKA_PAD

Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_CLKA_INBUF/U0/U0:PAD

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain CLK_LPC0

SET Register to Register

Path 1
  From:                        CORELPC_0/CLPCoII/CLPCLOil[4]:CLK
  To:                          CORELPC_0/CLPCoII/lad_OUt[0]/U1:D
  Delay (ns):                  7.082
  Slack (ns):
  Arrival (ns):                12.261
  Required (ns):
  Setup (ns):                  0.540
  Minimum Period (ns):         9.500

Path 2
  From:                        CORELPC_0/CLPCoII/CLPCLOil[3]:CLK
  To:                          CORELPC_0/CLPCoII/lad_OUt[0]/U1:D
  Delay (ns):                  7.195
  Slack (ns):
  Arrival (ns):                12.254
  Required (ns):
  Setup (ns):                  0.540
  Minimum Period (ns):         9.493

Path 3
  From:                        CORELPC_0/CLPCoII/CLPClLIL[14]/U1:CLK
  To:                          CORELPC_0/CLPCoII/CLPCLOil[17]:D
  Delay (ns):                  6.356
  Slack (ns):
  Arrival (ns):                12.949
  Required (ns):
  Setup (ns):                  0.540
  Minimum Period (ns):         9.428

Path 4
  From:                        CORELPC_0/CLPCoII/CLPCLOil[4]:CLK
  To:                          CORELPC_0/CLPCoII/lad_OUt[2]/U1:D
  Delay (ns):                  7.731
  Slack (ns):
  Arrival (ns):                12.910
  Required (ns):
  Setup (ns):                  0.540
  Minimum Period (ns):         9.103

Path 5
  From:                        CORELPC_0/CLPCoII/CLPCLOil[3]:CLK
  To:                          CORELPC_0/CLPCoII/lad_OUt[2]/U1:D
  Delay (ns):                  7.844
  Slack (ns):
  Arrival (ns):                12.903
  Required (ns):
  Setup (ns):                  0.540
  Minimum Period (ns):         9.096


Expanded Path 1
  From: CORELPC_0/CLPCoII/CLPCLOil[4]:CLK
  To: CORELPC_0/CLPCoII/lad_OUt[0]/U1:D
  data required time                             N/C
  data arrival time                          -   12.261
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK_LPC0
               +     0.000          Clock source
  0.000                        CLK_LPC0 (r)
               +     0.000          net: CLK_LPC0
  0.000                        CLK_LPC0_pad/U0/U0:PAD (r)
               +     0.806          cell: ADLIB:IOPAD_IN
  0.806                        CLK_LPC0_pad/U0/U0:Y (r)
               +     0.000          net: CLK_LPC0_pad/U0/NET1
  0.806                        CLK_LPC0_pad/U0/U1:YIN (r)
               +     0.033          cell: ADLIB:IOIN_IB
  0.839                        CLK_LPC0_pad/U0/U1:Y (r)
               +     4.340          net: CLK_LPC0_c
  5.179                        CORELPC_0/CLPCoII/CLPCLOil[4]:CLK (r)
               +     0.496          cell: ADLIB:DFN1C0
  5.675                        CORELPC_0/CLPCoII/CLPCLOil[4]:Q (f)
               +     0.282          net: CORELPC_0/CLPCoII/CLPCLOil[4]
  5.957                        CORELPC_0/CLPCoII/CLPCLOil_RNI7AIH[4]:A (f)
               +     0.385          cell: ADLIB:OR2
  6.342                        CORELPC_0/CLPCoII/CLPCLOil_RNI7AIH[4]:Y (f)
               +     1.385          net: CORELPC_0/CLPCoII/N_320
  7.727                        CORELPC_0/CLPCoII/CLPCLOil_RNI1PTB1[7]:B (f)
               +     0.493          cell: ADLIB:OR2
  8.220                        CORELPC_0/CLPCoII/CLPCLOil_RNI1PTB1[7]:Y (f)
               +     2.794          net: CORELPC_0/CLPCoII/N_325
  11.014                       CORELPC_0/CLPCoII/CLPCLOil_RNI7R382[17]:B (f)
               +     0.370          cell: ADLIB:NOR2A
  11.384                       CORELPC_0/CLPCoII/CLPCLOil_RNI7R382[17]:Y (r)
               +     0.237          net: CORELPC_0/CLPCoII/N_360
  11.621                       CORELPC_0/CLPCoII/lad_OUt[0]/U0:S (r)
               +     0.385          cell: ADLIB:MX2
  12.006                       CORELPC_0/CLPCoII/lad_OUt[0]/U0:Y (r)
               +     0.255          net: CORELPC_0/CLPCoII/lad_OUt[0]/Y
  12.261                       CORELPC_0/CLPCoII/lad_OUt[0]/U1:D (r)
                                    
  12.261                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK_LPC0
               +     0.000          Clock source
  N/C                          CLK_LPC0 (r)
               +     0.000          net: CLK_LPC0
  N/C                          CLK_LPC0_pad/U0/U0:PAD (r)
               +     0.806          cell: ADLIB:IOPAD_IN
  N/C                          CLK_LPC0_pad/U0/U0:Y (r)
               +     0.000          net: CLK_LPC0_pad/U0/NET1
  N/C                          CLK_LPC0_pad/U0/U1:YIN (r)
               +     0.033          cell: ADLIB:IOIN_IB
  N/C                          CLK_LPC0_pad/U0/U1:Y (r)
               +     2.462          net: CLK_LPC0_c
  N/C                          CORELPC_0/CLPCoII/lad_OUt[0]/U1:CLK (r)
               -     0.540          Library setup time: ADLIB:DFN1P0
  N/C                          CORELPC_0/CLPCoII/lad_OUt[0]/U1:D


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        LPC_LAD[3]
  To:                          CORELPC_0/CLPCoII/CLPCLOil[17]:D
  Delay (ns):                  9.912
  Slack (ns):
  Arrival (ns):                9.912
  Required (ns):
  Setup (ns):                  0.540
  External Setup (ns):         6.391

Path 2
  From:                        LPC_LAD[1]
  To:                          CORELPC_0/CLPCoII/CLPCLOil[17]:D
  Delay (ns):                  9.773
  Slack (ns):
  Arrival (ns):                9.773
  Required (ns):
  Setup (ns):                  0.540
  External Setup (ns):         6.252

Path 3
  From:                        LPC_LAD[3]
  To:                          CORELPC_0/CLPCoII/CLPCLOil[11]:D
  Delay (ns):                  9.053
  Slack (ns):
  Arrival (ns):                9.053
  Required (ns):
  Setup (ns):                  0.540
  External Setup (ns):         5.788

Path 4
  From:                        LPC_LAD[1]
  To:                          CORELPC_0/CLPCoII/CLPCLOil[11]:D
  Delay (ns):                  8.914
  Slack (ns):
  Arrival (ns):                8.914
  Required (ns):
  Setup (ns):                  0.540
  External Setup (ns):         5.649

Path 5
  From:                        LPC_LAD[3]
  To:                          CORELPC_0/CLPCoII/CLPCLOil[6]:D
  Delay (ns):                  9.181
  Slack (ns):
  Arrival (ns):                9.181
  Required (ns):
  Setup (ns):                  0.540
  External Setup (ns):         5.241


Expanded Path 1
  From: LPC_LAD[3]
  To: CORELPC_0/CLPCoII/CLPCLOil[17]:D
  data required time                             N/C
  data arrival time                          -   9.912
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        LPC_LAD[3] (f)
               +     0.000          net: LPC_LAD[3]
  0.000                        LPC_LAD_pad[3]/U0/U0:PAD (f)
               +     0.529          cell: ADLIB:IOPAD_BI
  0.529                        LPC_LAD_pad[3]/U0/U0:Y (f)
               +     0.000          net: LPC_LAD_pad[3]/U0/NET3
  0.529                        LPC_LAD_pad[3]/U0/U1:YIN (f)
               +     0.030          cell: ADLIB:IOBI_IB_OB_EB
  0.559                        LPC_LAD_pad[3]/U0/U1:Y (f)
               +     2.401          net: LPC_LAD_in[3]
  2.960                        CORELPC_0/CLPCoII/un20_lframen_2:B (f)
               +     0.749          cell: ADLIB:XOR2
  3.709                        CORELPC_0/CLPCoII/un20_lframen_2:Y (f)
               +     0.235          net: CORELPC_0/CLPCoII/un20_lframen_2
  3.944                        CORELPC_0/CLPCoII/CLPCLOil_ns_i_a2_3_1[0]:A (f)
               +     0.370          cell: ADLIB:NOR3
  4.314                        CORELPC_0/CLPCoII/CLPCLOil_ns_i_a2_3_1[0]:Y (r)
               +     1.171          net: CORELPC_0/CLPCoII/CLPCLOil_ns_i_a2_3_1[0]
  5.485                        CORELPC_0/CLPCoII/CLPCLOil_RNIGBUQ2[12]:A (r)
               +     0.398          cell: ADLIB:NOR3C
  5.883                        CORELPC_0/CLPCoII/CLPCLOil_RNIGBUQ2[12]:Y (r)
               +     0.279          net: CORELPC_0/CLPCoII/CLPCLOil_ns_i_a2_3_3[0]
  6.162                        CORELPC_0/CLPCoII/CLPCLOil_RNI0V4D4[12]:B (r)
               +     0.473          cell: ADLIB:NOR3C
  6.635                        CORELPC_0/CLPCoII/CLPCLOil_RNI0V4D4[12]:Y (r)
               +     1.220          net: CORELPC_0/CLPCoII/CLPCLOil_ns_i_a2_3_13[0]
  7.855                        CORELPC_0/CLPCoII/CLPCLOil_ns_i_a2_3[0]:A (r)
               +     0.370          cell: ADLIB:AND2
  8.225                        CORELPC_0/CLPCoII/CLPCLOil_ns_i_a2_3[0]:Y (r)
               +     0.247          net: CORELPC_0/CLPCoII/N_367
  8.472                        CORELPC_0/CLPCoII/CLPCLOil_ns_i_1[0]:C (r)
               +     0.486          cell: ADLIB:OR3
  8.958                        CORELPC_0/CLPCoII/CLPCLOil_ns_i_1[0]:Y (r)
               +     0.247          net: CORELPC_0/CLPCoII/CLPCLOil_ns_i_1[0]
  9.205                        CORELPC_0/CLPCoII/CLPCLOil_RNO[17]:B (r)
               +     0.460          cell: ADLIB:NOR3
  9.665                        CORELPC_0/CLPCoII/CLPCLOil_RNO[17]:Y (f)
               +     0.247          net: CORELPC_0/CLPCoII/CLPCLOil_RNO[17]
  9.912                        CORELPC_0/CLPCoII/CLPCLOil[17]:D (f)
                                    
  9.912                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK_LPC0
               +     0.000          Clock source
  N/C                          CLK_LPC0 (r)
               +     0.000          net: CLK_LPC0
  N/C                          CLK_LPC0_pad/U0/U0:PAD (r)
               +     0.806          cell: ADLIB:IOPAD_IN
  N/C                          CLK_LPC0_pad/U0/U0:Y (r)
               +     0.000          net: CLK_LPC0_pad/U0/NET1
  N/C                          CLK_LPC0_pad/U0/U1:YIN (r)
               +     0.033          cell: ADLIB:IOIN_IB
  N/C                          CLK_LPC0_pad/U0/U1:Y (r)
               +     3.222          net: CLK_LPC0_c
  N/C                          CORELPC_0/CLPCoII/CLPCLOil[17]:CLK (r)
               -     0.540          Library setup time: ADLIB:DFN1P0
  N/C                          CORELPC_0/CLPCoII/CLPCLOil[17]:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        CORELPC_0/CLPCoII/Lad_OEn/U1:CLK
  To:                          LPC_LAD[2]
  Delay (ns):                  6.375
  Slack (ns):
  Arrival (ns):                10.892
  Required (ns):
  Clock to Out (ns):           10.892

Path 2
  From:                        CORELPC_0/CLPCoII/lad_OUt[1]/U1:CLK
  To:                          LPC_LAD[1]
  Delay (ns):                  5.127
  Slack (ns):
  Arrival (ns):                10.137
  Required (ns):
  Clock to Out (ns):           10.137

Path 3
  From:                        CORELPC_0/CLPCoII/Lad_OEn/U1:CLK
  To:                          LPC_LAD[1]
  Delay (ns):                  5.524
  Slack (ns):
  Arrival (ns):                10.041
  Required (ns):
  Clock to Out (ns):           10.041

Path 4
  From:                        CORELPC_0/CLPCoII/Lad_OEn/U1:CLK
  To:                          LPC_LAD[0]
  Delay (ns):                  5.348
  Slack (ns):
  Arrival (ns):                9.865
  Required (ns):
  Clock to Out (ns):           9.865

Path 5
  From:                        CORELPC_0/CLPCoII/Lad_OEn/U1:CLK
  To:                          LPC_LAD[3]
  Delay (ns):                  5.348
  Slack (ns):
  Arrival (ns):                9.865
  Required (ns):
  Clock to Out (ns):           9.865


Expanded Path 1
  From: CORELPC_0/CLPCoII/Lad_OEn/U1:CLK
  To: LPC_LAD[2]
  data required time                             N/C
  data arrival time                          -   10.892
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        CLK_LPC0
               +     0.000          Clock source
  0.000                        CLK_LPC0 (r)
               +     0.000          net: CLK_LPC0
  0.000                        CLK_LPC0_pad/U0/U0:PAD (r)
               +     0.806          cell: ADLIB:IOPAD_IN
  0.806                        CLK_LPC0_pad/U0/U0:Y (r)
               +     0.000          net: CLK_LPC0_pad/U0/NET1
  0.806                        CLK_LPC0_pad/U0/U1:YIN (r)
               +     0.033          cell: ADLIB:IOIN_IB
  0.839                        CLK_LPC0_pad/U0/U1:Y (r)
               +     3.678          net: CLK_LPC0_c
  4.517                        CORELPC_0/CLPCoII/Lad_OEn/U1:CLK (r)
               +     0.399          cell: ADLIB:DFN1P0
  4.916                        CORELPC_0/CLPCoII/Lad_OEn/U1:Q (r)
               +     0.280          net: CORELPC_0_LAD_OEN
  5.196                        INTEL_RCC_FPGA_0/rcc_pwr_inst/rsm_rst_n_RNI744A:B (r)
               +     0.390          cell: ADLIB:NOR2A
  5.586                        INTEL_RCC_FPGA_0/rcc_pwr_inst/rsm_rst_n_RNI744A:Y (f)
               +     2.242          net: rsm_rst_n_RNI744A
  7.828                        LPC_LAD_pad[2]/U0/U1:E (f)
               +     0.316          cell: ADLIB:IOBI_IB_OB_EB
  8.144                        LPC_LAD_pad[2]/U0/U1:EOUT (f)
               +     0.000          net: LPC_LAD_pad[2]/U0/NET2
  8.144                        LPC_LAD_pad[2]/U0/U0:E (f)
               +     2.748          cell: ADLIB:IOPAD_BI
  10.892                       LPC_LAD_pad[2]/U0/U0:PAD (f)
               +     0.000          net: LPC_LAD[2]
  10.892                       LPC_LAD[2] (f)
                                    
  10.892                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK_LPC0
               +     0.000          Clock source
  N/C                          CLK_LPC0 (r)
                                    
  N/C                          LPC_LAD[2] (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

Path 1
  From:                        PLTRST_N
  To:                          CORELPC_0/CLPCoII/lad_OUt[0]/U1:PRE
  Delay (ns):                  6.891
  Slack (ns):
  Arrival (ns):                6.891
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      3.815

Path 2
  From:                        PLTRST_N
  To:                          CORELPC_0/CLPCoII/CLPClLIL[7]/U1:CLR
  Delay (ns):                  7.388
  Slack (ns):
  Arrival (ns):                7.388
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      3.335

Path 3
  From:                        PLTRST_N
  To:                          CORELPC_0/CLPCoII/CLPClLIL[4]/U1:CLR
  Delay (ns):                  6.887
  Slack (ns):
  Arrival (ns):                6.887
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      3.124

Path 4
  From:                        PLTRST_N
  To:                          CORELPC_0/CLPCoII/CLPCLOil[13]:CLR
  Delay (ns):                  7.400
  Slack (ns):
  Arrival (ns):                7.400
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      2.734

Path 5
  From:                        PLTRST_N
  To:                          CORELPC_0/CLPCoII/CLPCLOil[8]:CLR
  Delay (ns):                  5.816
  Slack (ns):
  Arrival (ns):                5.816
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      2.685


Expanded Path 1
  From: PLTRST_N
  To: CORELPC_0/CLPCoII/lad_OUt[0]/U1:PRE
  data required time                             N/C
  data arrival time                          -   6.891
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        PLTRST_N (r)
               +     0.000          net: PLTRST_N
  0.000                        PLTRST_N_pad/U0/U0:PAD (r)
               +     0.806          cell: ADLIB:IOPAD_IN
  0.806                        PLTRST_N_pad/U0/U0:Y (r)
               +     0.000          net: PLTRST_N_pad/U0/NET1
  0.806                        PLTRST_N_pad/U0/U1:YIN (r)
               +     0.033          cell: ADLIB:IOIN_IB
  0.839                        PLTRST_N_pad/U0/U1:Y (r)
               +     4.090          net: PLTRST_N_c
  4.929                        PLTRST_N_pad_RNIARJC_0:A (r)
               +     0.353          cell: ADLIB:BUFF
  5.282                        PLTRST_N_pad_RNIARJC_0:Y (r)
               +     1.609          net: PLTRST_N_c_0
  6.891                        CORELPC_0/CLPCoII/lad_OUt[0]/U1:PRE (r)
                                    
  6.891                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          CLK_LPC0
               +     0.000          Clock source
  N/C                          CLK_LPC0 (r)
               +     0.000          net: CLK_LPC0
  N/C                          CLK_LPC0_pad/U0/U0:PAD (r)
               +     0.806          cell: ADLIB:IOPAD_IN
  N/C                          CLK_LPC0_pad/U0/U0:Y (r)
               +     0.000          net: CLK_LPC0_pad/U0/NET1
  N/C                          CLK_LPC0_pad/U0/U1:YIN (r)
               +     0.033          cell: ADLIB:IOIN_IB
  N/C                          CLK_LPC0_pad/U0/U1:Y (r)
               +     2.462          net: CLK_LPC0_c
  N/C                          CORELPC_0/CLPCoII/lad_OUt[0]/U1:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1P0
  N/C                          CORELPC_0/CLPCoII/lad_OUt[0]/U1:PRE


END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q

SET Register to Register

Path 1
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[4]:CLK
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[14]:D
  Delay (ns):                  9.754
  Slack (ns):
  Arrival (ns):                12.622
  Required (ns):
  Setup (ns):                  0.540
  Minimum Period (ns):         11.493

Path 2
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[5]:CLK
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[14]:D
  Delay (ns):                  9.428
  Slack (ns):
  Arrival (ns):                12.296
  Required (ns):
  Setup (ns):                  0.540
  Minimum Period (ns):         11.167

Path 3
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[1]:CLK
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[15]:D
  Delay (ns):                  8.448
  Slack (ns):
  Arrival (ns):                11.633
  Required (ns):
  Setup (ns):                  0.540
  Minimum Period (ns):         10.504

Path 4
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[0]:CLK
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[15]:D
  Delay (ns):                  8.353
  Slack (ns):
  Arrival (ns):                11.538
  Required (ns):
  Setup (ns):                  0.540
  Minimum Period (ns):         10.409

Path 5
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[4]:CLK
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[13]:D
  Delay (ns):                  8.448
  Slack (ns):
  Arrival (ns):                11.316
  Required (ns):
  Setup (ns):                  0.540
  Minimum Period (ns):         10.187


Expanded Path 1
  From: INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[4]:CLK
  To: INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[14]:D
  data required time                             N/C
  data arrival time                          -   12.622
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q
               +     0.000          Clock source
  0.000                        INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q (r)
               +     2.868          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]
  2.868                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[4]:CLK (r)
               +     0.496          cell: ADLIB:DFN1C0
  3.364                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[4]:Q (f)
               +     2.350          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[4]
  5.714                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state_RNIGV0R[2]:A (f)
               +     0.370          cell: ADLIB:OR3
  6.084                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state_RNIGV0R[2]:Y (f)
               +     0.875          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/N_203
  6.959                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state_RNIDG542[2]:C (f)
               +     0.473          cell: ADLIB:NOR3A
  7.432                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state_RNIDG542[2]:Y (r)
               +     0.255          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/counter_n2_i_0_a2_2
  7.687                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state_RNI4SKV2[14]:B (r)
               +     0.473          cell: ADLIB:NOR3B
  8.160                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state_RNI4SKV2[14]:Y (r)
               +     0.255          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/counter_n2_i_0_a2_3
  8.415                        INTEL_RCC_FPGA_0/rcc_pwr_inst/timer_0_RNICD768:B (r)
               +     0.430          cell: ADLIB:AO1A
  8.845                        INTEL_RCC_FPGA_0/rcc_pwr_inst/timer_0_RNICD768:Y (r)
               +     2.253          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/N_512
  11.098                       INTEL_RCC_FPGA_0/rcc_pwr_inst/counter_RNO_0[14]:C (r)
               +     0.517          cell: ADLIB:OR3A
  11.615                       INTEL_RCC_FPGA_0/rcc_pwr_inst/counter_RNO_0[14]:Y (r)
               +     0.247          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/N_308
  11.862                       INTEL_RCC_FPGA_0/rcc_pwr_inst/counter_RNO[14]:A (r)
               +     0.505          cell: ADLIB:MX2C
  12.367                       INTEL_RCC_FPGA_0/rcc_pwr_inst/counter_RNO[14]:Y (f)
               +     0.255          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/counter_n14
  12.622                       INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[14]:D (f)
                                    
  12.622                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q (r)
               +     1.669          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[14]:CLK (r)
               -     0.540          Library setup time: ADLIB:DFN1C0
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[14]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        PMU_SLP_S45_N
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[14]:D
  Delay (ns):                  14.009
  Slack (ns):
  Arrival (ns):                14.009
  Required (ns):
  Setup (ns):                  0.540
  External Setup (ns):         12.880

Path 2
  From:                        PMU_SLP_S3_N
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[14]:D
  Delay (ns):                  13.282
  Slack (ns):
  Arrival (ns):                13.282
  Required (ns):
  Setup (ns):                  0.540
  External Setup (ns):         12.153

Path 3
  From:                        PMU_SLP_S45_N
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[13]:D
  Delay (ns):                  12.703
  Slack (ns):
  Arrival (ns):                12.703
  Required (ns):
  Setup (ns):                  0.540
  External Setup (ns):         11.574

Path 4
  From:                        PMU_SLP_S45_N
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[15]:D
  Delay (ns):                  12.687
  Slack (ns):
  Arrival (ns):                12.687
  Required (ns):
  Setup (ns):                  0.540
  External Setup (ns):         11.558

Path 5
  From:                        PMU_SLP_S45_N
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[9]:D
  Delay (ns):                  12.539
  Slack (ns):
  Arrival (ns):                12.539
  Required (ns):
  Setup (ns):                  0.540
  External Setup (ns):         11.510


Expanded Path 1
  From: PMU_SLP_S45_N
  To: INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[14]:D
  data required time                             N/C
  data arrival time                          -   14.009
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        PMU_SLP_S45_N (f)
               +     0.000          net: PMU_SLP_S45_N
  0.000                        PMU_SLP_S45_N_pad/U0/U0:PAD (f)
               +     0.558          cell: ADLIB:IOPAD_IN
  0.558                        PMU_SLP_S45_N_pad/U0/U0:Y (f)
               +     0.000          net: PMU_SLP_S45_N_pad/U0/NET1
  0.558                        PMU_SLP_S45_N_pad/U0/U1:YIN (f)
               +     0.030          cell: ADLIB:IOIN_IB
  0.588                        PMU_SLP_S45_N_pad/U0/U1:Y (f)
               +     2.385          net: PMU_SLP_S45_N_c
  2.973                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pwr_state_proc.un1_pmu_slp_s3_n:B (f)
               +     0.479          cell: ADLIB:NOR2B
  3.452                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pwr_state_proc.un1_pmu_slp_s3_n:Y (f)
               +     3.952          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/un1_pmu_slp_s3_n
  7.404                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state_RNIMOD01[7]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  7.883                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state_RNIMOD01[7]:Y (f)
               +     0.308          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/N_295
  8.191                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state_RNIIN1T1[12]:C (f)
               +     0.535          cell: ADLIB:AO1
  8.726                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state_RNIIN1T1[12]:Y (f)
               +     0.247          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/next_timer_iv_0_0_o2_0
  8.973                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state_RNIGVG05[12]:C (f)
               +     0.570          cell: ADLIB:OR3
  9.543                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state_RNIGVG05[12]:Y (f)
               +     0.295          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/N_197
  9.838                        INTEL_RCC_FPGA_0/rcc_pwr_inst/timer_0_RNICD768:A (f)
               +     0.394          cell: ADLIB:AO1A
  10.232                       INTEL_RCC_FPGA_0/rcc_pwr_inst/timer_0_RNICD768:Y (r)
               +     2.253          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/N_512
  12.485                       INTEL_RCC_FPGA_0/rcc_pwr_inst/counter_RNO_0[14]:C (r)
               +     0.517          cell: ADLIB:OR3A
  13.002                       INTEL_RCC_FPGA_0/rcc_pwr_inst/counter_RNO_0[14]:Y (r)
               +     0.247          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/N_308
  13.249                       INTEL_RCC_FPGA_0/rcc_pwr_inst/counter_RNO[14]:A (r)
               +     0.505          cell: ADLIB:MX2C
  13.754                       INTEL_RCC_FPGA_0/rcc_pwr_inst/counter_RNO[14]:Y (f)
               +     0.255          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/counter_n14
  14.009                       INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[14]:D (f)
                                    
  14.009                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q (r)
               +     1.669          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[14]:CLK (r)
               -     0.540          Library setup time: ADLIB:DFN1C0
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/counter[14]:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/S5_event:CLK
  To:                          CPU_PWRBTN_N
  Delay (ns):                  8.364
  Slack (ns):
  Arrival (ns):                9.944
  Required (ns):
  Clock to Out (ns):           9.944

Path 2
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/rsm_rst_n:CLK
  To:                          LPC_LAD[2]
  Delay (ns):                  8.041
  Slack (ns):
  Arrival (ns):                9.627
  Required (ns):
  Clock to Out (ns):           9.627

Path 3
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/ddr_vcca_pwrok:CLK
  To:                          DDR3_VCCA_PWROK
  Delay (ns):                  6.376
  Slack (ns):
  Arrival (ns):                9.256
  Required (ns):
  Clock to Out (ns):           9.256

Path 4
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/rsm_rst_n:CLK
  To:                          LPC_LAD[1]
  Delay (ns):                  7.096
  Slack (ns):
  Arrival (ns):                8.682
  Required (ns):
  Clock to Out (ns):           8.682

Path 5
  From:                        INTEL_RCC_FPGA_0/rcc_pwr_inst/rsm_rst_n:CLK
  To:                          LPC_LAD[0]
  Delay (ns):                  6.972
  Slack (ns):
  Arrival (ns):                8.558
  Required (ns):
  Clock to Out (ns):           8.558


Expanded Path 1
  From: INTEL_RCC_FPGA_0/rcc_pwr_inst/S5_event:CLK
  To: CPU_PWRBTN_N
  data required time                             N/C
  data arrival time                          -   9.944
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q
               +     0.000          Clock source
  0.000                        INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q (r)
               +     1.580          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]
  1.580                        INTEL_RCC_FPGA_0/rcc_pwr_inst/S5_event:CLK (r)
               +     0.496          cell: ADLIB:DFN1E1P0
  2.076                        INTEL_RCC_FPGA_0/rcc_pwr_inst/S5_event:Q (f)
               +     0.958          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/S5_event
  3.034                        INTEL_RCC_FPGA_0/rcc_pwr_inst/S5_event_RNIR0MN:B (f)
               +     0.479          cell: ADLIB:NOR2B
  3.513                        INTEL_RCC_FPGA_0/rcc_pwr_inst/S5_event_RNIR0MN:Y (f)
               +     0.255          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/un4_cpu_pwrbtn_n_0
  3.768                        INTEL_RCC_FPGA_0/rcc_pwr_inst/S5_event_RNITQUD1:C (f)
               +     0.517          cell: ADLIB:NOR3C
  4.285                        INTEL_RCC_FPGA_0/rcc_pwr_inst/S5_event_RNITQUD1:Y (f)
               +     2.351          net: S5_event_RNITQUD1
  6.636                        CPU_PWRBTN_N_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  7.136                        CPU_PWRBTN_N_pad/U0/U1:DOUT (f)
               +     0.000          net: CPU_PWRBTN_N_pad/U0/NET1
  7.136                        CPU_PWRBTN_N_pad/U0/U0:D (f)
               +     2.808          cell: ADLIB:IOPAD_TRI
  9.944                        CPU_PWRBTN_N_pad/U0/U0:PAD (f)
               +     0.000          net: CPU_PWRBTN_N_0
  9.944                        CPU_PWRBTN_N (f)
                                    
  9.944                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q (r)
                                    
  N/C                          CPU_PWRBTN_N (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

Path 1
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[3]:CLR
  Delay (ns):                  1.550
  Slack (ns):
  Arrival (ns):                1.550
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      1.337

Path 2
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/v1p1_en:CLR
  Delay (ns):                  1.518
  Slack (ns):
  Arrival (ns):                1.518
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      1.305

Path 3
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/clr_thermtrip_latch:PRE
  Delay (ns):                  1.518
  Slack (ns):
  Arrival (ns):                1.518
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      1.305

Path 4
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/v1p35_en:CLR
  Delay (ns):                  1.507
  Slack (ns):
  Arrival (ns):                1.507
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      1.294

Path 5
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/v12_pcie_en:CLR
  Delay (ns):                  1.507
  Slack (ns):
  Arrival (ns):                1.507
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      0.840


Expanded Path 1
  From: FPGA_RESET_N
  To: INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[3]:CLR
  data required time                             N/C
  data arrival time                          -   1.550
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        FPGA_RESET_N (r)
               +     0.000          net: FPGA_RESET_N
  0.000                        FPGA_RESET_N_pad/U0/U0:PAD (r)
               +     0.806          cell: ADLIB:IOPAD_IN
  0.806                        FPGA_RESET_N_pad/U0/U0:Y (r)
               +     0.000          net: FPGA_RESET_N_pad/U0/NET1
  0.806                        FPGA_RESET_N_pad/U0/U1:A (r)
               +     0.262          cell: ADLIB:CLKSRC
  1.068                        FPGA_RESET_N_pad/U0/U1:Y (r)
               +     0.482          net: FPGA_RESET_N_c
  1.550                        INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[3]:CLR (r)
                                    
  1.550                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]:Q (r)
               +     0.438          net: INTEL_RCC_FPGA_0/rcc_pwr_inst/div_counter[8]
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[3]:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1C0
  N/C                          INTEL_RCC_FPGA_0/rcc_pwr_inst/pm_state[3]:CLR


END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_aclk

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_fabric_interface_clock

SET Register to Register

Path 1
  From:                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6]
  Delay (ns):                  27.908
  Slack (ns):
  Arrival (ns):                27.908
  Required (ns):
  Setup (ns):                  -1.879
  Minimum Period (ns):         26.029

Path 2
  From:                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[7]
  Delay (ns):                  27.060
  Slack (ns):
  Arrival (ns):                27.060
  Required (ns):
  Setup (ns):                  -1.874
  Minimum Period (ns):         25.186

Path 3
  From:                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[1]
  Delay (ns):                  26.845
  Slack (ns):
  Arrival (ns):                26.845
  Required (ns):
  Setup (ns):                  -1.853
  Minimum Period (ns):         24.992

Path 4
  From:                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[5]
  Delay (ns):                  26.605
  Slack (ns):
  Arrival (ns):                26.605
  Required (ns):
  Setup (ns):                  -1.870
  Minimum Period (ns):         24.735

Path 5
  From:                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[4]
  Delay (ns):                  25.983
  Slack (ns):
  Arrival (ns):                25.983
  Required (ns):
  Setup (ns):                  -1.871
  Minimum Period (ns):         24.112


Expanded Path 1
  From: INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GLB
  To: INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6]
  data required time                             N/C
  data arrival time                          -   27.908
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_fabric_interface_clock
               +     0.000          Clock source
  0.000                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               +     3.040          cell: ADLIB:MSS_APB_IP
  3.040                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPADDR[6] (f)
               +     0.131          net: INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/MSSPADDR[6]INT_NET
  3.171                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_32:PIN1INT (f)
               +     0.073          cell: ADLIB:MSS_IF
  3.244                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_32:PIN1 (f)
               +     3.218          net: CoreAPB3_0_APBmslave0_PADDR[6]
  6.462                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST_RNIIM6_2:A (f)
               +     0.385          cell: ADLIB:BUFF
  6.847                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST_RNIIM6_2:Y (f)
               +     1.911          net: CoreAPB3_0_APBmslave0_PADDR_0_0[6]
  8.758                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST_RNIIM6_37:A (f)
               +     0.407          cell: ADLIB:BUFF
  9.165                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST_RNIIM6_37:Y (f)
               +     2.724          net: CoreAPB3_0_APBmslave0_PADDR_1[6]
  11.889                       CoreGPIO_0/CGPIOiOI.0.CGPIOO1I.CGPIOOIa24:C (f)
               +     0.517          cell: ADLIB:NOR3C
  12.406                       CoreGPIO_0/CGPIOiOI.0.CGPIOO1I.CGPIOOIa24:Y (f)
               +     0.291          net: CoreGPIO_0/CGPIOOIa24
  12.697                       CoreGPIO_0/CGPIOiOI.0.CGPIOO1I.CGPIOOIrff_24_RNI4ETE:B (f)
               +     0.476          cell: ADLIB:NOR2B
  13.173                       CoreGPIO_0/CGPIOiOI.0.CGPIOO1I.CGPIOOIrff_24_RNI4ETE:Y (f)
               +     0.892          net: CoreGPIO_0/CGPIOOIria_24
  14.065                       CoreGPIO_0/CGPIOiOI.0.CGPIOO1I.CGPIOOIrff_12_RNICMLR1:B (f)
               +     0.473          cell: ADLIB:OR3
  14.538                       CoreGPIO_0/CGPIOiOI.0.CGPIOO1I.CGPIOOIrff_12_RNICMLR1:Y (f)
               +     1.516          net: CoreGPIO_0/CGPIOOIror_16
  16.054                       CoreGPIO_0/CGPIOiOI.0.CGPIOO1I.CGPIOOIrff_12_RNI0FB27:B (f)
               +     0.473          cell: ADLIB:OR3
  16.527                       CoreGPIO_0/CGPIOiOI.0.CGPIOO1I.CGPIOOIrff_12_RNI0FB27:Y (f)
               +     0.255          net: CoreGPIO_0/CGPIOOIror_28
  16.782                       CoreGPIO_0/CGPIOiOI.0.CGPIOO1I.CGPIOOIrff_4_RNICGKVC:B (f)
               +     0.493          cell: ADLIB:OR2
  17.275                       CoreGPIO_0/CGPIOiOI.0.CGPIOO1I.CGPIOOIrff_4_RNICGKVC:Y (f)
               +     1.806          net: CoreGPIO_0/CGPIOOIror
  19.081                       CoreGPIO_0/CGPIOiOI.0.CGPIOO1I.CGPIOOIrff_4_RNIU6RVC:A (f)
               +     0.479          cell: ADLIB:NOR2A
  19.560                       CoreGPIO_0/CGPIOiOI.0.CGPIOO1I.CGPIOOIrff_4_RNIU6RVC:Y (f)
               +     1.360          net: CoreGPIO_0/N_165
  20.920                       CoreGPIO_0/CGPIOiOI.0.CGPIOO1I.CGPIOOI_CGPIOiOI.0.CGPIOO1I.CGPIOOI_ram17__RNIO3URK[6]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  21.399                       CoreGPIO_0/CGPIOiOI.0.CGPIOO1I.CGPIOOI_CGPIOiOI.0.CGPIOO1I.CGPIOOI_ram17__RNIO3URK[6]:Y (f)
               +     0.267          net: CoreGPIO_0_N_129
  21.666                       CoreAPB3_0/CAPB3OOl1/m44:A (f)
               +     0.482          cell: ADLIB:OA1
  22.148                       CoreAPB3_0/CAPB3OOl1/m44:Y (f)
               +     1.623          net: CoreAPB3_0/CAPB3OOl1/N_45
  23.771                       CoreAPB3_0/CAPB3OOl1/m46:A (f)
               +     0.439          cell: ADLIB:MX2C
  24.210                       CoreAPB3_0/CAPB3OOl1/m46:Y (r)
               +     0.754          net: CoreAPB3_0/CAPB3OOl1/N_47
  24.964                       CoreAPB3_0/CAPB3OOl1/m50:A (r)
               +     0.505          cell: ADLIB:MX2C
  25.469                       CoreAPB3_0/CAPB3OOl1/m50:Y (f)
               +     1.943          net: CoreAPB3_0_N_51
  27.412                       INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_38:PIN6 (f)
               +     0.145          cell: ADLIB:MSS_IF
  27.557                       INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_38:PIN6INT (f)
               +     0.351          net: INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/MSSPRDATA[6]INT_NET
  27.908                       INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6] (f)
                                    
  27.908                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_fabric_interface_clock
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GLB (r)
               -    -1.879          Library setup time: ADLIB:MSS_APB_IP
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSPRDATA[6]


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_pclk1

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        GPIO_24_IN
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[24]
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  0.500
  External Setup (ns):         1.281

Path 2
  From:                        GPIO_26_IN
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[26]
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  0.480
  External Setup (ns):         1.261

Path 3
  From:                        GPIO_27_IN
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[27]
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  0.290
  External Setup (ns):         1.071

Path 4
  From:                        GPIO_25_IN
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[25]
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  0.054
  External Setup (ns):         0.835

Path 5
  From:                        GPIO_28_IN
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[28]
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  0.023
  External Setup (ns):         0.804


Expanded Path 1
  From: GPIO_24_IN
  To: INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[24]
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        GPIO_24_IN (r)
               +     0.000          net: GPIO_24_IN
  0.000                        INTEL_RCC_FPGA_X100_MSS_0/MSS_GPIO_0_GPIO_24_IN:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        INTEL_RCC_FPGA_X100_MSS_0/MSS_GPIO_0_GPIO_24_IN:Y (r)
               +     0.000          net: INTEL_RCC_FPGA_X100_MSS_0/MSS_GPIO_0_GPIO_24_IN_Y
  0.781                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[24] (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_pclk1
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:PCLK1 (r)
               -     0.500          Library setup time: ADLIB:MSS_APB_IP
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:GPI[24]


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_gla0

Info: The maximum frequency of this clock domain is limited by the period of pin INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK

SET Register to Register

No Path

END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        MSS_RESET_N
  To:                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  Delay (ns):                  0.781
  Slack (ns):
  Arrival (ns):                0.781
  Required (ns):
  Setup (ns):                  -1.830
  External Setup (ns):         -1.574


Expanded Path 1
  From: MSS_RESET_N
  To: INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn
  data required time                             N/C
  data arrival time                          -   0.781
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        MSS_RESET_N (r)
               +     0.000          net: MSS_RESET_N
  0.000                        INTEL_RCC_FPGA_X100_MSS_0/MSS_RESET_0_MSS_RESET_N:PAD (r)
               +     0.781          cell: ADLIB:IOPAD_IN
  0.781                        INTEL_RCC_FPGA_X100_MSS_0/MSS_RESET_0_MSS_RESET_N:Y (r)
               +     0.000          net: INTEL_RCC_FPGA_X100_MSS_0/MSS_RESET_0_MSS_RESET_N_Y
  0.781                        INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn (r)
                                    
  0.781                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_gla0
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLAMSS (r)
               +     0.525          net: INTEL_RCC_FPGA_X100_MSS_0/GLA0
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:FCLK (r)
               -    -1.830          Library setup time: ADLIB:MSS_APB_IP
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_ADLIB_INST/U_CORE:MSSRESETn


END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Clock Domain mss_ccc_glb

SET Register to Register

Path 1
  From:                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter[0]:CLK
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/counter[30]:D
  Delay (ns):                  31.891
  Slack (ns):
  Arrival (ns):                32.414
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         32.320

Path 2
  From:                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter[1]:CLK
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/counter[30]:D
  Delay (ns):                  31.749
  Slack (ns):
  Arrival (ns):                32.272
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         32.178

Path 3
  From:                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter[0]:CLK
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/counter[29]:D
  Delay (ns):                  31.032
  Slack (ns):
  Arrival (ns):                31.555
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         31.452

Path 4
  From:                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter[2]:CLK
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/counter[30]:D
  Delay (ns):                  30.960
  Slack (ns):
  Arrival (ns):                31.483
  Required (ns):
  Setup (ns):                  0.409
  Minimum Period (ns):         31.389

Path 5
  From:                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter[1]:CLK
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/counter[29]:D
  Delay (ns):                  30.890
  Slack (ns):
  Arrival (ns):                31.413
  Required (ns):
  Setup (ns):                  0.435
  Minimum Period (ns):         31.310


Expanded Path 1
  From: INTEL_RCC_FPGA_0/rcc_spi_inst/counter[0]:CLK
  To: INTEL_RCC_FPGA_0/rcc_spi_inst/counter[30]:D
  data required time                             N/C
  data arrival time                          -   32.414
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.523          net: FAB_CLK
  0.523                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter[0]:CLK (r)
               +     0.559          cell: ADLIB:DFN1C0
  1.082                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter[0]:Q (f)
               +     0.336          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter[0]
  1.418                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI7BSM[1]:B (f)
               +     0.476          cell: ADLIB:NOR2B
  1.894                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI7BSM[1]:Y (f)
               +     0.308          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c1
  2.202                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNICIA21[2]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  2.681                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNICIA21[2]:Y (f)
               +     0.956          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c2
  3.637                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIIQOD1[3]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  4.116                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIIQOD1[3]:Y (f)
               +     0.308          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c3
  4.424                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIP37P1[4]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  4.903                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIP37P1[4]:Y (f)
               +     0.308          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c4
  5.211                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI1EL42[5]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  5.690                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI1EL42[5]:Y (f)
               +     0.308          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c5
  5.998                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIAP3G2[6]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  6.477                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIAP3G2[6]:Y (f)
               +     1.024          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c6
  7.501                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIK5IR2[7]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  7.980                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIK5IR2[7]:Y (f)
               +     0.308          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c7
  8.288                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIVI073[8]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  8.767                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIVI073[8]:Y (f)
               +     0.308          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c8
  9.075                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIB1FI3[9]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  9.554                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIB1FI3[9]:Y (f)
               +     0.308          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c9
  9.862                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIVV1S3[10]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  10.341                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIVV1S3[10]:Y (f)
               +     1.412          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c10
  11.753                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIKVK54[11]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  12.232                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIKVK54[11]:Y (f)
               +     0.308          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c11
  12.540                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIA08F4[12]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  13.019                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIA08F4[12]:Y (f)
               +     0.308          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c12
  13.327                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI12RO4[13]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  13.806                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI12RO4[13]:Y (f)
               +     0.308          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c13
  14.114                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIP4E25[14]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  14.593                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIP4E25[14]:Y (f)
               +     0.308          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c14
  14.901                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNII81C5[15]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  15.380                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNII81C5[15]:Y (f)
               +     0.308          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c15
  15.688                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNICDKL5[16]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  16.167                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNICDKL5[16]:Y (f)
               +     0.308          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c16
  16.475                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI7J7V5[17]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  16.954                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI7J7V5[17]:Y (f)
               +     1.690          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c17
  18.644                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI3QQ86[18]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  19.123                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI3QQ86[18]:Y (f)
               +     0.308          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c18
  19.431                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI02EI6[19]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  19.910                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI02EI6[19]:Y (f)
               +     0.308          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c19
  20.218                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIL22S6[20]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  20.697                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIL22S6[20]:Y (f)
               +     1.333          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c20
  22.030                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIB4M57[21]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  22.509                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIB4M57[21]:Y (f)
               +     0.310          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c21
  22.819                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI27AF7[22]:A (f)
               +     0.293          cell: ADLIB:NOR2B
  23.112                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI27AF7[22]:Y (f)
               +     1.050          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c22
  24.162                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIQAUO7[23]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  24.641                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIQAUO7[23]:Y (f)
               +     0.322          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c23
  24.963                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIJFI28[24]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  25.442                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIJFI28[24]:Y (f)
               +     0.308          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c24
  25.750                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIDL6C8[25]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  26.229                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNIDL6C8[25]:Y (f)
               +     0.308          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c25
  26.537                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI8SQL8[26]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  27.016                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI8SQL8[26]:Y (f)
               +     1.909          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c26
  28.925                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI44FV8[27]:B (f)
               +     0.479          cell: ADLIB:NOR2B
  29.404                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI44FV8[27]:Y (f)
               +     0.299          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c27
  29.703                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI1D399[28]:A (f)
               +     0.293          cell: ADLIB:NOR2B
  29.996                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNI1D399[28]:Y (f)
               +     0.687          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_c28
  30.683                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNO_0[30]:A (f)
               +     0.753          cell: ADLIB:AX1C
  31.436                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNO_0[30]:Y (f)
               +     0.247          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_n30_tz
  31.683                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNO[30]:A (f)
               +     0.476          cell: ADLIB:NOR2A
  32.159                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter_RNO[30]:Y (f)
               +     0.255          net: INTEL_RCC_FPGA_0/rcc_spi_inst/counter_n30
  32.414                       INTEL_RCC_FPGA_0/rcc_spi_inst/counter[30]:D (f)
                                    
  32.414                       data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.503          net: FAB_CLK
  N/C                          INTEL_RCC_FPGA_0/rcc_spi_inst/counter[30]:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1C0
  N/C                          INTEL_RCC_FPGA_0/rcc_spi_inst/counter[30]:D


END SET Register to Register

----------------------------------------------------

SET External Setup

Path 1
  From:                        GPIO_CPU_SUS7
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/sreg[0]:D
  Delay (ns):                  8.671
  Slack (ns):
  Arrival (ns):                8.671
  Required (ns):
  Setup (ns):                  0.409
  External Setup (ns):         8.543

Path 2
  From:                        GPIO_CPU_SUS7
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/sreg[1]:D
  Delay (ns):                  7.096
  Slack (ns):
  Arrival (ns):                7.096
  Required (ns):
  Setup (ns):                  0.409
  External Setup (ns):         6.968

Path 3
  From:                        FPGA_JMPR1
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/sreg[0]:D
  Delay (ns):                  6.714
  Slack (ns):
  Arrival (ns):                6.714
  Required (ns):
  Setup (ns):                  0.409
  External Setup (ns):         6.586

Path 4
  From:                        PLTRST_N
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/reg_boot_ok:D
  Delay (ns):                  6.116
  Slack (ns):
  Arrival (ns):                6.116
  Required (ns):
  Setup (ns):                  0.409
  External Setup (ns):         6.022

Path 5
  From:                        FPGA_JMPR1
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/reg_boot_ok:D
  Delay (ns):                  5.753
  Slack (ns):
  Arrival (ns):                5.753
  Required (ns):
  Setup (ns):                  0.409
  External Setup (ns):         5.659


Expanded Path 1
  From: GPIO_CPU_SUS7
  To: INTEL_RCC_FPGA_0/rcc_spi_inst/sreg[0]:D
  data required time                             N/C
  data arrival time                          -   8.671
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        GPIO_CPU_SUS7 (f)
               +     0.000          net: GPIO_CPU_SUS7
  0.000                        GPIO_CPU_SUS7_pad/U0/U0:PAD (f)
               +     0.558          cell: ADLIB:IOPAD_IN
  0.558                        GPIO_CPU_SUS7_pad/U0/U0:Y (f)
               +     0.000          net: GPIO_CPU_SUS7_pad/U0/NET1
  0.558                        GPIO_CPU_SUS7_pad/U0/U1:YIN (f)
               +     0.030          cell: ADLIB:IOIN_IB
  0.588                        GPIO_CPU_SUS7_pad/U0/U1:Y (f)
               +     4.158          net: GPIO_CPU_SUS7_c
  4.746                        INTEL_RCC_FPGA_0/rcc_spi_inst/sreg_RNO_6[0]:A (f)
               +     0.479          cell: ADLIB:NOR2A
  5.225                        INTEL_RCC_FPGA_0/rcc_spi_inst/sreg_RNO_6[0]:Y (f)
               +     1.273          net: INTEL_RCC_FPGA_0/rcc_spi_inst/next_sreg_0_iv_0_0_a2_1_0[0]
  6.498                        INTEL_RCC_FPGA_0/rcc_spi_inst/sreg_RNO_2[0]:B (f)
               +     0.486          cell: ADLIB:NOR3C
  6.984                        INTEL_RCC_FPGA_0/rcc_spi_inst/sreg_RNO_2[0]:Y (f)
               +     0.247          net: INTEL_RCC_FPGA_0/rcc_spi_inst/N_176
  7.231                        INTEL_RCC_FPGA_0/rcc_spi_inst/sreg_RNO[0]:C (f)
               +     0.570          cell: ADLIB:NOR3
  7.801                        INTEL_RCC_FPGA_0/rcc_spi_inst/sreg_RNO[0]:Y (r)
               +     0.870          net: INTEL_RCC_FPGA_0/rcc_spi_inst/next_sreg_0_iv[0]
  8.671                        INTEL_RCC_FPGA_0/rcc_spi_inst/sreg[0]:D (r)
                                    
  8.671                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.537          net: FAB_CLK
  N/C                          INTEL_RCC_FPGA_0/rcc_spi_inst/sreg[0]:CLK (r)
               -     0.409          Library setup time: ADLIB:DFN1E0C0
  N/C                          INTEL_RCC_FPGA_0/rcc_spi_inst/sreg[0]:D


END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        CoreGPIO_1/CGPIOo0[1]:CLK
  To:                          CPU_PWRBTN_N
  Delay (ns):                  7.281
  Slack (ns):
  Arrival (ns):                7.834
  Required (ns):
  Clock to Out (ns):           7.834

Path 2
  From:                        INTEL_RCC_FPGA_0/rcc_spi_inst/serial_data_out:CLK
  To:                          GPIO_CPU_SUS2
  Delay (ns):                  5.189
  Slack (ns):
  Arrival (ns):                5.750
  Required (ns):
  Clock to Out (ns):           5.750

Path 3
  From:                        INTEL_RCC_FPGA_0/rcc_spi_inst/spi_mux:CLK
  To:                          SPI_CS_SELECT
  Delay (ns):                  4.803
  Slack (ns):
  Arrival (ns):                5.340
  Required (ns):
  Clock to Out (ns):           5.340


Expanded Path 1
  From: CoreGPIO_1/CGPIOo0[1]:CLK
  To: CPU_PWRBTN_N
  data required time                             N/C
  data arrival time                          -   7.834
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        mss_ccc_glb
               +     0.000          Clock source
  0.000                        INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  0.000                        INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  0.000                        INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.553          net: FAB_CLK
  0.553                        CoreGPIO_1/CGPIOo0[1]:CLK (r)
               +     0.559          cell: ADLIB:DFN1E1P0
  1.112                        CoreGPIO_1/CGPIOo0[1]:Q (f)
               +     0.790          net: GPIO_OUT_net_0[1]
  1.902                        INTEL_RCC_FPGA_0/rcc_pwr_inst/S5_event_RNITQUD1:A (f)
               +     0.273          cell: ADLIB:NOR3C
  2.175                        INTEL_RCC_FPGA_0/rcc_pwr_inst/S5_event_RNITQUD1:Y (f)
               +     2.351          net: S5_event_RNITQUD1
  4.526                        CPU_PWRBTN_N_pad/U0/U1:D (f)
               +     0.500          cell: ADLIB:IOTRI_OB_EB
  5.026                        CPU_PWRBTN_N_pad/U0/U1:DOUT (f)
               +     0.000          net: CPU_PWRBTN_N_pad/U0/NET1
  5.026                        CPU_PWRBTN_N_pad/U0/U0:D (f)
               +     2.808          cell: ADLIB:IOPAD_TRI
  7.834                        CPU_PWRBTN_N_pad/U0/U0:PAD (f)
               +     0.000          net: CPU_PWRBTN_N_0
  7.834                        CPU_PWRBTN_N (f)
                                    
  7.834                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
                                    
  N/C                          CPU_PWRBTN_N (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

Path 1
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/counter[4]:CLR
  Delay (ns):                  1.546
  Slack (ns):
  Arrival (ns):                1.546
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      1.294

Path 2
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/counter[5]:CLR
  Delay (ns):                  1.544
  Slack (ns):
  Arrival (ns):                1.544
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      1.285

Path 3
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/thermtrip_n_3:CLR
  Delay (ns):                  1.550
  Slack (ns):
  Arrival (ns):                1.550
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      1.285

Path 4
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_pwr_inst/thermtrip_latch:PRE
  Delay (ns):                  1.550
  Slack (ns):
  Arrival (ns):                1.550
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      1.285

Path 5
  From:                        FPGA_RESET_N
  To:                          INTEL_RCC_FPGA_0/rcc_spi_inst/counter[6]:CLR
  Delay (ns):                  1.544
  Slack (ns):
  Arrival (ns):                1.544
  Required (ns):
  Recovery (ns):               0.225
  External Recovery (ns):      1.285


Expanded Path 1
  From: FPGA_RESET_N
  To: INTEL_RCC_FPGA_0/rcc_spi_inst/counter[4]:CLR
  data required time                             N/C
  data arrival time                          -   1.546
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        FPGA_RESET_N (r)
               +     0.000          net: FPGA_RESET_N
  0.000                        FPGA_RESET_N_pad/U0/U0:PAD (r)
               +     0.806          cell: ADLIB:IOPAD_IN
  0.806                        FPGA_RESET_N_pad/U0/U0:Y (r)
               +     0.000          net: FPGA_RESET_N_pad/U0/NET1
  0.806                        FPGA_RESET_N_pad/U0/U1:A (r)
               +     0.262          cell: ADLIB:CLKSRC
  1.068                        FPGA_RESET_N_pad/U0/U1:Y (r)
               +     0.478          net: FPGA_RESET_N_c
  1.546                        INTEL_RCC_FPGA_0/rcc_spi_inst/counter[4]:CLR (r)
                                    
  1.546                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          mss_ccc_glb
               +     0.000          Clock source
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_MSSCCC:GLB (r)
               +     0.000          net: INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/GLB_INT
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5INT (r)
               +     0.000          cell: ADLIB:MSS_CCC_GL_IF
  N/C                          INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE2:PIN5 (r)
               +     0.477          net: FAB_CLK
  N/C                          INTEL_RCC_FPGA_0/rcc_spi_inst/counter[4]:CLK (r)
               -     0.225          Library recovery time: ADLIB:DFN1C0
  N/C                          INTEL_RCC_FPGA_0/rcc_spi_inst/counter[4]:CLR


END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path

END SET Asynchronous to Register

----------------------------------------------------

Path set Pin to Pin

SET Input to Output

Path 1
  From:                        PM_V3P3_PWRGD
  To:                          SMB_PECI_DATA
  Delay (ns):                  9.746
  Slack (ns):
  Arrival (ns):                9.746
  Required (ns):

Path 2
  From:                        PM_V3P3_PWRGD
  To:                          SMB_PECI_CLK
  Delay (ns):                  9.623
  Slack (ns):
  Arrival (ns):                9.623
  Required (ns):

Path 3
  From:                        PM_V3P3_PWRGD
  To:                          SMB_3V3_HOST_ALERT_N
  Delay (ns):                  9.490
  Slack (ns):
  Arrival (ns):                9.490
  Required (ns):

Path 4
  From:                        PM_V3P3_PWRGD
  To:                          IRQ_ILB_SERIRQ_CPU
  Delay (ns):                  8.565
  Slack (ns):
  Arrival (ns):                8.565
  Required (ns):

Path 5
  From:                        FP_PWR_BTN_N
  To:                          CPU_PWRBTN_N
  Delay (ns):                  8.410
  Slack (ns):
  Arrival (ns):                8.410
  Required (ns):


Expanded Path 1
  From: PM_V3P3_PWRGD
  To: SMB_PECI_DATA
  data required time                             N/C
  data arrival time                          -   9.746
  slack                                          N/C
  ________________________________________________________
  Data arrival time calculation
  0.000                        PM_V3P3_PWRGD (f)
               +     0.000          net: PM_V3P3_PWRGD
  0.000                        PM_V3P3_PWRGD_pad/U0/U0:PAD (f)
               +     0.558          cell: ADLIB:IOPAD_IN
  0.558                        PM_V3P3_PWRGD_pad/U0/U0:Y (f)
               +     0.000          net: PM_V3P3_PWRGD_pad/U0/NET1
  0.558                        PM_V3P3_PWRGD_pad/U0/U1:YIN (f)
               +     0.030          cell: ADLIB:IOIN_IB
  0.588                        PM_V3P3_PWRGD_pad/U0/U1:Y (f)
               +     2.274          net: PM_V3P3_PWRGD_c
  2.862                        PM_V3P3_PWRGD_pad_RNIV53A:A (f)
               +     0.407          cell: ADLIB:INV
  3.269                        PM_V3P3_PWRGD_pad_RNIV53A:Y (r)
               +     3.362          net: PM_V3P3_PWRGD_c_i
  6.631                        SMB_PECI_DATA_pad/U0/U1:E (r)
               +     0.355          cell: ADLIB:IOTRI_OB_EB
  6.986                        SMB_PECI_DATA_pad/U0/U1:EOUT (r)
               +     0.000          net: SMB_PECI_DATA_pad/U0/NET2
  6.986                        SMB_PECI_DATA_pad/U0/U0:E (r)
               +     2.760          cell: ADLIB:IOPAD_TRI
  9.746                        SMB_PECI_DATA_pad/U0/U0:PAD (f)
               +     0.000          net: SMB_PECI_DATA_0
  9.746                        SMB_PECI_DATA (f)
                                    
  9.746                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          PM_V3P3_PWRGD (f)
                                    
  N/C                          SMB_PECI_DATA (f)
                                    
  N/C                          data required time


END SET Input to Output

----------------------------------------------------

Path set User Sets

