********************************************************************
                            Global Net Report
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Product: Designer
Release: v11.5
Version: 11.5.0.26
Date: Tue Feb 03 16:42:52 2015
Design Name: INTEL_RCC_FPGA_X100  Family: SmartFusion  Die: A2F200M3F  Package: 256 FBGA


Automatic Global Net Placement Result:
Status: Global net placement completed successfully


Global Nets Information:

        |--------------------------------------------------------------------------------------------------|
        |Global Nets                                                      |Loads                           |
        |--------------------------------------------------------------------------------------------------|
        |Name                                                             |Core      |IO        |RAM       |
        |--------------------------------------------------------------------------------------------------|
        |CLOCK_MACRO: INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1|        0 |        0 |        0 |
        |--------------------------------------------------------------------------------------------------|
        |CoreAPB3_0_APBmslave0_PADDR[2]                                   |      299 |        0 |        0 |
        |--------------------------------------------------------------------------------------------------|
        |FAB_CLK                                                          |     1077 |        0 |        0 |
        |--------------------------------------------------------------------------------------------------|
        |FPGA_RESET_N_c                                                   |      132 |        0 |        0 |
        |--------------------------------------------------------------------------------------------------|
        |INTEL_RCC_FPGA_X100_MSS_0_M2F_RESET_N                            |      717 |        0 |        0 |
        |--------------------------------------------------------------------------------------------------|

Nets Sharing Loads:

        |-----------------------------------------------------------------------------------------------------------------------------------|
        |Global Net                                                       |Shares Loads With ...                                            |
        |-----------------------------------------------------------------------------------------------------------------------------------|
        |FAB_CLK                                                          |FPGA_RESET_N_c                                                   |
        |                                                                 |INTEL_RCC_FPGA_X100_MSS_0_M2F_RESET_N                            |
        |-----------------------------------------------------------------------------------------------------------------------------------|
        |FPGA_RESET_N_c                                                   |FAB_CLK                                                          |
        |-----------------------------------------------------------------------------------------------------------------------------------|
        |INTEL_RCC_FPGA_X100_MSS_0_M2F_RESET_N                            |FAB_CLK                                                          |
        |-----------------------------------------------------------------------------------------------------------------------------------|

Summary of Global Net Placement:

        |---------------------------------------------------------------------------------------------------------------------|
        |Global Net                                                       |Assignment          |Violation                     |
        |---------------------------------------------------------------------------------------------------------------------|
        |CLOCK_MACRO: INTEL_RCC_FPGA_X100_MSS_0/MSS_CCC_0/I_MSSCCC/U_TILE1|MIDDLE_LEFT         |                              |
        |---------------------------------------------------------------------------------------------------------------------|
        |CoreAPB3_0_APBmslave0_PADDR[2]                                   |MIDDLE_RIGHT        |                              |
        |---------------------------------------------------------------------------------------------------------------------|
        |FAB_CLK                                                          |MIDDLE_LEFT         |                              |
        |---------------------------------------------------------------------------------------------------------------------|
        |FPGA_RESET_N_c                                                   |UPPER_LEFT          |                              |
        |---------------------------------------------------------------------------------------------------------------------|
        |INTEL_RCC_FPGA_X100_MSS_0_M2F_RESET_N                            |MIDDLE_RIGHT        |                              |
        |---------------------------------------------------------------------------------------------------------------------|
