| Project Settings |
|---|
| Project Name | proj_1 | Device Name | Denverton_COMe_CPLD: Lattice MachXO2 : LCMXO2_1200HC |
| Implementation Name | Denverton_COMe_CPLD | Top Module | COME_CPLD_TOP |
| Pipelining | 1 | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 1000 |
| Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
| Clock Conversion | 1 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
67 |
118 |
0 |
- |
00m:00s |
- |
2021/5/24
11:28:55 |
| (premap) | Error |
0 |
0 |
1 |
0m:00s |
0m:00s |
128MB |
2021/5/24
11:28:56 |
| (fpga_mapper) | out-of-date |
41 |
2 |
0 |
0m:05s |
0m:06s |
180MB |
2020/4/4
10:49:46 |
| Area Summary |
|---|
|
| Register bits | 465 |
I/O cells | 67 |
| Block RAMs
(v_ram) | 0 |
DSPs
(dsp_used) | 0 |
| ORCA LUTs
(total_luts) | 413 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| COME_CPLD_TOP|LPC_CLK | 1.0 MHz | 167.7 MHz | 994.037 |
| COME_CPLD_TOP|clk_sys_inferred_clock | 66.5 MHz | 77.3 MHz | 2.095 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 1 / 1 |
| |
|