Synthesis and Ngdbuild Report
synthesis: version Diamond (64-bit) 3.12.0.240.2
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Mon May 24 11:28:35 2021
Command Line: synthesis -f Denverton_COMe_CPLD_Denverton_COMe_CPLD_lattice.synproj -gui -msgset E:/work/COMe/C3000/COMe_V06/promote.xml
Synthesis options:
The -a option is MachXO2.
The -s option is 4.
The -t option is TQFP100.
The -d option is LCMXO2-1200HC.
Using package TQFP100.
Using performance grade 4.
##########################################################
### Lattice Family : MachXO2
### Device : LCMXO2-1200HC
### Package : TQFP100
### Speed : 4
##########################################################
INFO - synthesis: User-Selected Strategy Settings
Optimization goal = Area
Top-level module name = COME_CPLD_TOP.
Target frequency = 1.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3 (default)
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1
Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = TRUE
Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = no
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p E:/work/COMe/C3000/COMe_V06 (searchpath added)
-p E:/lattice 3.12/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
-p E:/work/COMe/C3000/COMe_V06/Denverton_COMe_CPLD (searchpath added)
-p E:/work/COMe/C3000/COMe_V06 (searchpath added)
Verilog design file = E:/work/COMe/C3000/COMe_V06/Denverton_COMe_CPLD/source/cfg_int_gen.v
Verilog design file = E:/work/COMe/C3000/COMe_V06/Denverton_COMe_CPLD/source/COME_CPLD_TOP.v
Verilog design file = E:/work/COMe/C3000/COMe_V06/Denverton_COMe_CPLD/source/LPC_IO_CYCLE.v
Verilog design file = E:/work/COMe/C3000/COMe_V06/Denverton_COMe_CPLD/source/power_seq.v
Verilog design file = E:/work/COMe/C3000/COMe_V06/Denverton_COMe_CPLD/source/Wd_Ctrl_Mod.v
NGD file = Denverton_COMe_CPLD_Denverton_COMe_CPLD.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...
Analyzing Verilog file E:/lattice 3.12/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file e:/work/come/c3000/come_v06/denverton_come_cpld/source/cfg_int_gen.v. VERI-1482
Analyzing Verilog file e:/work/come/c3000/come_v06/denverton_come_cpld/source/come_cpld_top.v. VERI-1482
Analyzing Verilog file e:/work/come/c3000/come_v06/denverton_come_cpld/source/lpc_io_cycle.v. VERI-1482
Analyzing Verilog file e:/work/come/c3000/come_v06/denverton_come_cpld/source/power_seq.v. VERI-1482
Analyzing Verilog file e:/work/come/c3000/come_v06/denverton_come_cpld/source/wd_ctrl_mod.v. VERI-1482
Analyzing Verilog file E:/lattice 3.12/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): COME_CPLD_TOP
INFO - synthesis: e:/work/come/c3000/come_v06/denverton_come_cpld/source/come_cpld_top.v(19): compiling module COME_CPLD_TOP. VERI-1018
INFO - synthesis: E:/lattice 3.12/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793): compiling module OSCH(NOM_FREQ="66.50"). VERI-1018
INFO - synthesis: e:/work/come/c3000/come_v06/denverton_come_cpld/source/lpc_io_cycle.v(2): compiling module LPC_IO_CYCLE(IO_RANGE_LOW=12'b101000011110,IO_RANGE_HIGH=12'b101000011111). VERI-1018
INFO - synthesis: e:/work/come/c3000/come_v06/denverton_come_cpld/source/power_seq.v(20): compiling module power_seq. VERI-1018
WARNING - synthesis: e:/work/come/c3000/come_v06/denverton_come_cpld/source/power_seq.v(276): expression size 32 truncated to fit in target size 8. VERI-1209
WARNING - synthesis: e:/work/come/c3000/come_v06/denverton_come_cpld/source/power_seq.v(286): expression size 32 truncated to fit in target size 9. VERI-1209
INFO - synthesis: e:/work/come/c3000/come_v06/denverton_come_cpld/source/wd_ctrl_mod.v(1): compiling module Wd_Ctrl_Mod. VERI-1018
INFO - synthesis: e:/work/come/c3000/come_v06/denverton_come_cpld/source/cfg_int_gen.v(1): compiling module cfg_int_gen(DI_WIDTH=4'b0101). VERI-1018
Loading NGL library 'E:/lattice 3.12/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'E:/lattice 3.12/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'E:/lattice 3.12/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'E:/lattice 3.12/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c1200.nph' in environment: E:/lattice 3.12/diamond/3.12/ispfpga.
Package Status: Final Version 1.42.
Top-level module name = COME_CPLD_TOP.
WARNING - synthesis: I/O Port EXCD0_CPPE_N 's net has no driver and is unused.
WARNING - synthesis: I/O Port EXCD0_PERST_N 's net has no driver and is unused.
WARNING - synthesis: I/O Port EXCD1_CPPE_N 's net has no driver and is unused.
WARNING - synthesis: I/O Port EXCD1_PERST_N 's net has no driver and is unused.
WARNING - synthesis: I/O Port I2C_SCL 's net has no driver and is unused.
WARNING - synthesis: I/O Port CPLD_PROCHOT_L 's net has no driver and is unused.
WARNING - synthesis: I/O Port THRM_N 's net has no driver and is unused.
WARNING - synthesis: I/O Port VCCP_PINALRT 's net has no driver and is unused.
WARNING - synthesis: I/O Port VDDQP_PINALRT 's net has no driver and is unused.
WARNING - synthesis: I/O Port VDDQP_PGOOD 's net has no driver and is unused.
WARNING - synthesis: I/O Port XP0R6V_PGOOD 's net has no driver and is unused.
WARNING - synthesis: e:/work/come/c3000/come_v06/denverton_come_cpld/source/cfg_int_gen.v(47): Register \int_Interrupt0/int_di_r1[3]_365 is stuck at One. VDB-5014
WARNING - synthesis: e:/work/come/c3000/come_v06/denverton_come_cpld/source/cfg_int_gen.v(58): Register \int_Interrupt0/int_status[3]_366 is stuck at One. VDB-5014
WARNING - synthesis: e:/work/come/c3000/come_v06/denverton_come_cpld/source/cfg_int_gen.v(73): Register \int_Interrupt0/int_status_r1[3]_367 is stuck at One. VDB-5014
WARNING - synthesis: e:/work/come/c3000/come_v06/denverton_come_cpld/source/cfg_int_gen.v(73): Register \int_Interrupt0/int_status_neg[3]_370 is stuck at Zero. VDB-5013
WARNING - synthesis: e:/work/come/c3000/come_v06/denverton_come_cpld/source/cfg_int_gen.v(103): Register \int_Interrupt0/int_trig_neg[3]_372 is stuck at One. VDB-5014
WARNING - synthesis: e:/work/come/c3000/come_v06/denverton_come_cpld/source/cfg_int_gen.v(118): Register \int_Interrupt0/int_trig_level[3]_373 is stuck at One. VDB-5014
WARNING - synthesis: e:/work/come/c3000/come_v06/denverton_come_cpld/source/cfg_int_gen.v(88): Register \int_Interrupt0/int_trig_pos[3]_371 is stuck at One. VDB-5014
WARNING - synthesis: e:/work/come/c3000/come_v06/denverton_come_cpld/source/cfg_int_gen.v(168): Register \int_Interrupt0/int_do_temp[3]_374 is stuck at One. VDB-5014
INFO - synthesis: Extracted state machine for register '\LPC_inst1/data_read_count' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
0000 -> 0000000000000001
0001 -> 0000000000000010
0010 -> 0000000000000100
0011 -> 0000000000001000
0100 -> 0000000000010000
0101 -> 0000000000100000
0110 -> 0000000001000000
0111 -> 0000000010000000
1000 -> 0000000100000000
1001 -> 0000001000000000
1010 -> 0000010000000000
1011 -> 0000100000000000
1100 -> 0001000000000000
1101 -> 0010000000000000
1110 -> 0100000000000000
1111 -> 1000000000000000
INFO - synthesis: Extracted state machine for register '\LPC_inst1/cur_state' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
000001 -> 000001
000010 -> 000010
000100 -> 000100
001000 -> 001000
010000 -> 010000
100000 -> 100000
INFO - synthesis: Extracted state machine for register '\power_seq_inst1/current_state' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
0000000000000 -> 0000000000000000000000000001
0000000000001 -> 0000000000000000000000000010
0000000000010 -> 0000000000000000000000000100
0000000000011 -> 0000000000000000000000001000
0000000000100 -> 0000000000000000000000010000
0000000000101 -> 0000000000000000000000100000
0000000000110 -> 0000000000000000000001000000
0000000000111 -> 0000000000000000000010000000
0000000001000 -> 0000000000000000000100000000
0000000001001 -> 0000000000000000001000000000
0000000001010 -> 0000000000000000010000000000
0000000001011 -> 0000000000000000100000000000
0000000001100 -> 0000000000000001000000000000
0000000001111 -> 0000000000000010000000000000
0000000010000 -> 0000000000000100000000000000
0000000010001 -> 0000000000001000000000000000
0000000010010 -> 0000000000010000000000000000
0000000010011 -> 0000000000100000000000000000
0000000010100 -> 0000000001000000000000000000
0000000010101 -> 0000000010000000000000000000
0000000010110 -> 0000000100000000000000000000
0000000010111 -> 0000001000000000000000000000
0000000011000 -> 0000010000000000000000000000
0000000011001 -> 0000100000000000000000000000
0000000011010 -> 0001000000000000000000000000
0000000011011 -> 0010000000000000000000000000
0000000011100 -> 0100000000000000000000000000
0000000011101 -> 1000000000000000000000000000
INFO - synthesis: Extracted state machine for register '\Wd_Ctrl_Mod_inst1/s_current_sta' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
0001 -> 0001
0010 -> 0010
0100 -> 0100
1000 -> 1000
WARNING - synthesis: Bit 13 of Register \power_seq_inst1/current_state_FSM is stuck at Zero
WARNING - synthesis: I/O Port EXCD0_CPPE_N 's net has no driver and is unused.
WARNING - synthesis: I/O Port EXCD0_PERST_N 's net has no driver and is unused.
WARNING - synthesis: I/O Port EXCD1_CPPE_N 's net has no driver and is unused.
WARNING - synthesis: I/O Port EXCD1_PERST_N 's net has no driver and is unused.
WARNING - synthesis: I/O Port I2C_SCL 's net has no driver and is unused.
WARNING - synthesis: I/O Port CPLD_PROCHOT_L 's net has no driver and is unused.
WARNING - synthesis: I/O Port THRM_N 's net has no driver and is unused.
WARNING - synthesis: I/O Port VCCP_PINALRT 's net has no driver and is unused.
WARNING - synthesis: I/O Port VDDQP_PINALRT 's net has no driver and is unused.
WARNING - synthesis: I/O Port VDDQP_PGOOD 's net has no driver and is unused.
WARNING - synthesis: I/O Port XP0R6V_PGOOD 's net has no driver and is unused.
Duplicate register/latch removal. \power_seq_inst1/o_xp0r6v_en_521 is a one-to-one match with \power_seq_inst1/o_xp1r24v_en_523.
INFO - synthesis: Register L_VRHOT_T_i0_i0 of type IFS1P3BX will not be replicated.
INFO - synthesis: Register L_THERMTRIP_N_CON_i0_i0 of type IFS1P3BX will not be replicated.
INFO - synthesis: Register L_CPLD_MEMHOT_L_i0_i0 of type IFS1P3BX will not be replicated.
INFO - synthesis: Register L_IRQ_DIMM_EVENT_L_i0_i0 of type IFS1P3BX will not be replicated.
INFO - synthesis: Register \power_seq_inst1/s_xp1r8v_pgood_i0_i0 of type IFS1P3DX will not be replicated.
INFO - synthesis: Register \power_seq_inst1/s_vnnp_pgood_i0_i0 of type IFS1P3DX will not be replicated.
INFO - synthesis: Register \power_seq_inst1/s_xp1r05v_pgood_i0_i0 of type IFS1P3DX will not be replicated.
INFO - synthesis: Register \power_seq_inst1/s_xp2r5v_pgood_i0_i0 of type IFS1P3DX will not be replicated.
INFO - synthesis: Register \power_seq_inst1/s_xp1r24v_pgood_i0_i0 of type IFS1P3DX will not be replicated.
INFO - synthesis: Register \power_seq_inst1/s_vccp_pgood_i0_i0 of type IFS1P3DX will not be replicated.
INFO - synthesis: Register \power_seq_inst1/s_vccramp_pgood_i0_i0 of type IFS1P3DX will not be replicated.
INFO - synthesis: Register \LPC_inst1/lad_i_r_i0 of type IFS1P3DX will not be replicated.
INFO - synthesis: Register \LPC_inst1/lad_i_r_i3 of type IFS1P3DX will not be replicated.
INFO - synthesis: Register \LPC_inst1/lad_i_r_i2 of type IFS1P3DX will not be replicated.
INFO - synthesis: Register \LPC_inst1/lad_i_r_i1 of type IFS1P3DX will not be replicated.
Applying 1.000000 MHz constraint to all clocks
Results of NGD DRC are available in COME_CPLD_TOP_drc.log.
Loading NGL library 'E:/lattice 3.12/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'E:/lattice 3.12/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'E:/lattice 3.12/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'E:/lattice 3.12/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
WARNING - synthesis: logical net 'EXCD0_CPPE_N' has no load.
WARNING - synthesis: input pad net 'EXCD0_CPPE_N' has no legal load.
WARNING - synthesis: logical net 'EXCD0_PERST_N' has no load.
WARNING - synthesis: input pad net 'EXCD0_PERST_N' has no legal load.
WARNING - synthesis: logical net 'EXCD1_CPPE_N' has no load.
WARNING - synthesis: input pad net 'EXCD1_CPPE_N' has no legal load.
WARNING - synthesis: logical net 'EXCD1_PERST_N' has no load.
WARNING - synthesis: input pad net 'EXCD1_PERST_N' has no legal load.
WARNING - synthesis: logical net 'I2C_SCL' has no load.
WARNING - synthesis: input pad net 'I2C_SCL' has no legal load.
WARNING - synthesis: logical net 'CPLD_PROCHOT_L' has no load.
WARNING - synthesis: input pad net 'CPLD_PROCHOT_L' has no legal load.
WARNING - synthesis: logical net 'THRM_N' has no load.
WARNING - synthesis: input pad net 'THRM_N' has no legal load.
WARNING - synthesis: logical net 'VCCP_PINALRT' has no load.
WARNING - synthesis: input pad net 'VCCP_PINALRT' has no legal load.
WARNING - synthesis: logical net 'VDDQP_PINALRT' has no load.
WARNING - synthesis: input pad net 'VDDQP_PINALRT' has no legal load.
WARNING - synthesis: logical net 'VDDQP_PGOOD' has no load.
WARNING - synthesis: input pad net 'VDDQP_PGOOD' has no legal load.
WARNING - synthesis: logical net 'XP0R6V_PGOOD' has no load.
WARNING - synthesis: input pad net 'XP0R6V_PGOOD' has no legal load.
WARNING - synthesis: DRC complete with 22 warnings.
All blocks are expanded and NGD expansion is successful.
Writing NGD file Denverton_COMe_CPLD_Denverton_COMe_CPLD.ngd.
################### Begin Area Report (COME_CPLD_TOP)######################
Number of register bits => 599 of 1520 (39 % )
BB => 4
CCU2D => 203
FD1P3AX => 1
FD1P3BX => 41
FD1P3DX => 111
FD1S3AX => 6
FD1S3BX => 15
FD1S3DX => 396
FD1S3IX => 1
GSR => 1
IB => 24
IFS1P3BX => 4
IFS1P3DX => 11
LUT4 => 486
OB => 18
OBZ => 19
OFS1P3BX => 1
OFS1P3DX => 12
OSCH => 1
PFUMX => 13
################### End Area Report ##################
################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################
################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 2
Net : clk_sys, loads : 538
Net : LPC_CLK_c, loads : 61
Clock Enable Nets
Number of Clock Enables: 39
Top 10 highest fanout Clock Enables:
Net : power_seq_inst1/s_base_1ms_pulse, loads : 22
Net : LPC_inst1/cur_state_3, loads : 17
Net : LPC_inst1/LPC_CLK_c_enable_29, loads : 16
Net : Wd_Ctrl_Mod_inst1/s_pulse_100ms, loads : 14
Net : power_seq_inst1/clk_sys_enable_43, loads : 10
Net : s_lpc_rd_en, loads : 10
Net : Wd_Ctrl_Mod_inst1/clk_sys_enable_32, loads : 8
Net : Wd_Ctrl_Mod_inst1/clk_sys_enable_35, loads : 6
Net : power_seq_inst1/i_pmu_slp_s45_n, loads : 5
Net : LPC_inst1/LPC_CLK_c_enable_21, loads : 4
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
Net : int_Interrupt0/i_rst_N_228, loads : 529
Net : LPC_inst1/lpc_lad_o_3__N_31, loads : 61
Net : power_seq_inst1/s_base_1ms_pulse, loads : 44
Net : power_seq_inst1/n848, loads : 32
Net : power_seq_inst1/n1007, loads : 31
Net : power_seq_inst1/n976, loads : 31
Net : power_seq_inst1/n985, loads : 31
Net : power_seq_inst1/n857, loads : 31
Net : power_seq_inst1/n979, loads : 31
Net : power_seq_inst1/n982, loads : 31
################### End Clock Report ##################
Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint | Constraint| Actual|Levels
--------------------------------------------------------------------------------
| | |
create_clock -period 1000.000000 -name | | |
clk1 [get_nets LPC_CLK_c] | 1.000 MHz| 101.348 MHz| 6
| | |
create_clock -period 1000.000000 -name | | |
clk0 [get_nets clk_sys] | 1.000 MHz| 50.518 MHz| 25
| | |
--------------------------------------------------------------------------------
All constraints were met.
Peak Memory Usage: 79.328 MB
--------------------------------------------------------------
Elapsed CPU time for LSE flow : 3.172 secs
--------------------------------------------------------------