@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MO111 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\come_cpld_top.v":138:19:138:22|Tristate driver SOC_ERR2_N (in view: work.COME_CPLD_TOP(verilog)) on net SOC_ERR2_N (in view: work.COME_CPLD_TOP(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\come_cpld_top.v":138:19:138:22|Tristate driver SOC_ERR1_N (in view: work.COME_CPLD_TOP(verilog)) on net SOC_ERR1_N (in view: work.COME_CPLD_TOP(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\come_cpld_top.v":138:19:138:22|Tristate driver SOC_ERR0_N (in view: work.COME_CPLD_TOP(verilog)) on net SOC_ERR0_N (in view: work.COME_CPLD_TOP(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\come_cpld_top.v":138:19:138:22|Tristate driver SLEEP_CPLD_N (in view: work.COME_CPLD_TOP(verilog)) on net SLEEP_CPLD_N (in view: work.COME_CPLD_TOP(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\come_cpld_top.v":138:19:138:22|Tristate driver SATA0_LED_N (in view: work.COME_CPLD_TOP(verilog)) on net SATA0_LED_N (in view: work.COME_CPLD_TOP(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\come_cpld_top.v":138:19:138:22|Tristate driver FM_SOC_FPGA_MCERR_N (in view: work.COME_CPLD_TOP(verilog)) on net FM_SOC_FPGA_MCERR_N (in view: work.COME_CPLD_TOP(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\come_cpld_top.v":138:19:138:22|Tristate driver FM_SOC_CATERR_N (in view: work.COME_CPLD_TOP(verilog)) on net FM_SOC_CATERR_N (in view: work.COME_CPLD_TOP(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\come_cpld_top.v":138:19:138:22|Tristate driver FLEX_CLK_SE_0 (in view: work.COME_CPLD_TOP(verilog)) on net FLEX_CLK_SE_0 (in view: work.COME_CPLD_TOP(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\come_cpld_top.v":138:19:138:22|Tristate driver FAULT1_VDDQP (in view: work.COME_CPLD_TOP(verilog)) on net FAULT1_VDDQP (in view: work.COME_CPLD_TOP(verilog)) has its enable tied to GND.
@N: MO111 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\come_cpld_top.v":138:19:138:22|Tristate driver FAULT1_VCCP (in view: work.COME_CPLD_TOP(verilog)) on net FAULT1_VCCP (in view: work.COME_CPLD_TOP(verilog)) has its enable tied to GND.
@N: MO231 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\come_cpld_top.v":171:0:171:5|Found counter in view:work.COME_CPLD_TOP(verilog) instance internal_por_cnt[4:0] 
@N: BN362 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\lpc_io_cycle.v":201:4:201:9|Removing sequential instance data_addr[15] (in view: work.LPC_IO_CYCLE_Z1(verilog)) because it does not drive other instances.
@N: BN362 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\lpc_io_cycle.v":201:4:201:9|Removing sequential instance data_addr[14] (in view: work.LPC_IO_CYCLE_Z1(verilog)) because it does not drive other instances.
@N: BN362 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\lpc_io_cycle.v":201:4:201:9|Removing sequential instance data_addr[13] (in view: work.LPC_IO_CYCLE_Z1(verilog)) because it does not drive other instances.
@N: BN362 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\lpc_io_cycle.v":201:4:201:9|Removing sequential instance data_addr[12] (in view: work.LPC_IO_CYCLE_Z1(verilog)) because it does not drive other instances.
@N: MO231 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\lpc_io_cycle.v":100:4:100:9|Found counter in view:work.LPC_IO_CYCLE_Z1(verilog) instance data_write_count[3:0] 
@N: MO231 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\lpc_io_cycle.v":83:4:83:9|Found counter in view:work.LPC_IO_CYCLE_Z1(verilog) instance data_read_count[3:0] 
@N: MO231 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\power_seq.v":314:0:314:5|Found counter in view:work.power_seq(verilog) instance seq_power_cnt[31:0] 
@N: MO231 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\power_seq.v":259:0:259:5|Found counter in view:work.power_seq(verilog) instance V1P80_CNT[17:0] 
@N: MO231 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\power_seq.v":247:0:247:5|Found counter in view:work.power_seq(verilog) instance VNN_CNT[17:0] 
@N: MO231 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\power_seq.v":235:0:235:5|Found counter in view:work.power_seq(verilog) instance V1P05_CNT[17:0] 
@N: MO231 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\power_seq.v":223:0:223:5|Found counter in view:work.power_seq(verilog) instance RSMRST_N_CNT[17:0] 
@N: MO231 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\power_seq.v":211:0:211:5|Found counter in view:work.power_seq(verilog) instance VDDQ_N_CNT[17:0] 
@N: MO231 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\power_seq.v":199:0:199:5|Found counter in view:work.power_seq(verilog) instance VCCREF_CNT[17:0] 
@N: MO231 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\power_seq.v":187:0:187:5|Found counter in view:work.power_seq(verilog) instance VCCRAM_CNT[17:0] 
@N: MO231 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\power_seq.v":175:0:175:5|Found counter in view:work.power_seq(verilog) instance VCC_EN_CNT[17:0] 
@N: MO231 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\power_seq.v":163:0:163:5|Found counter in view:work.power_seq(verilog) instance power_ok_CNT[17:0] 
@N: MO231 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\power_seq.v":271:0:271:5|Found counter in view:work.power_seq(verilog) instance S_count_base0[7:0] 
@N: MO225 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\wd_ctrl_mod.v":142:0:142:5|There are no possible illegal states for state machine s_current_sta[3:0] (in view: work.Wd_Ctrl_Mod(verilog)); safe FSM implementation is not required.
@N: MO231 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\wd_ctrl_mod.v":42:0:42:5|Found counter in view:work.Wd_Ctrl_Mod(verilog) instance s_cnt_100ms[6:0] 
@N: MO231 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\wd_ctrl_mod.v":175:0:175:5|Found counter in view:work.Wd_Ctrl_Mod(verilog) instance s_loss_count[10:0] 
@N: MO231 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\wd_ctrl_mod.v":72:0:72:5|Found counter in view:work.Wd_Ctrl_Mod(verilog) instance s_cnt_5s[5:0] 
@N: MF179 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\wd_ctrl_mod.v":156:27:156:52|Found 8 by 8 bit equality operator ('==') un1_i_wd_dly_set (in view: work.Wd_Ctrl_Mod(verilog))
@N: BN362 :"e:\ydc\cpld\questone 2\2.pld\data\20190120-debug\cpld\come_debug\come_v06\denverton_come_cpld\source\cfg_int_gen.v":121:6:121:11|Removing sequential instance int_Interrupt0.loop\[3\]\.int_do_temp[3] (in view: work.COME_CPLD_TOP(verilog)) because it does not drive other instances.
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: FX1056 |Writing EDF file: E:\ydc\cpld\Questone 2\2.PLD\Data\20190120-debug\cpld\come_debug\COMe_V06\Denverton_COMe_CPLD\Denverton_COMe_CPLD_Denverton_COMe_CPLD.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
