Setting log file to 'E:/work/COMe/C3000/COMe_V06/Denverton_COMe_CPLD/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file 'E:/lattice 3.12/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
(VERI-1482) Analyzing Verilog file 'E:/work/COMe/C3000/COMe_V06/Denverton_COMe_CPLD/source/cfg_int_gen.v'
(VERI-1482) Analyzing Verilog file 'E:/work/COMe/C3000/COMe_V06/Denverton_COMe_CPLD/source/COME_CPLD_TOP.v'
(VERI-1482) Analyzing Verilog file 'E:/work/COMe/C3000/COMe_V06/Denverton_COMe_CPLD/source/LPC_IO_CYCLE.v'
(VERI-1482) Analyzing Verilog file 'E:/work/COMe/C3000/COMe_V06/Denverton_COMe_CPLD/source/power_seq.v'
(VERI-1482) Analyzing Verilog file 'E:/work/COMe/C3000/COMe_V06/Denverton_COMe_CPLD/source/Wd_Ctrl_Mod.v'
INFO - E:/work/COMe/C3000/COMe_V06/Denverton_COMe_CPLD/source/COME_CPLD_TOP.v(19,8-19,21) (VERI-1018) compiling module 'COME_CPLD_TOP'
INFO - E:/work/COMe/C3000/COMe_V06/Denverton_COMe_CPLD/source/COME_CPLD_TOP.v(19,1-463,10) (VERI-9000) elaborating module 'COME_CPLD_TOP'
INFO - E:/lattice 3.12/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793,1-1798,10) (VERI-9000) elaborating module 'OSCH_uniq_1'
INFO - E:/work/COMe/C3000/COMe_V06/Denverton_COMe_CPLD/source/LPC_IO_CYCLE.v(2,1-336,10) (VERI-9000) elaborating module 'LPC_IO_CYCLE_uniq_1'
INFO - E:/work/COMe/C3000/COMe_V06/Denverton_COMe_CPLD/source/power_seq.v(20,1-835,10) (VERI-9000) elaborating module 'power_seq_uniq_1'
INFO - E:/work/COMe/C3000/COMe_V06/Denverton_COMe_CPLD/source/Wd_Ctrl_Mod.v(1,1-196,10) (VERI-9000) elaborating module 'Wd_Ctrl_Mod_uniq_1'
INFO - E:/work/COMe/C3000/COMe_V06/Denverton_COMe_CPLD/source/cfg_int_gen.v(1,1-176,10) (VERI-9000) elaborating module 'cfg_int_gen_uniq_1'
Done: design load finished with (0) errors, and (0) warnings