Place & Route TRACE Report
Loading design for application trce from file denverton_come_cpld_denverton_come_cpld.ncd.
Design name: COME_CPLD_TOP
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.10_x64/ispfpga.
Package Status: Final Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.10.3.144
Sat Apr 04 10:50:13 2020
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Denverton_COMe_CPLD_Denverton_COMe_CPLD.twr -gui -msgset E:/ydc/cpld/Questone 2/2.PLD/Data/20190120-debug/cpld/come_debug/COMe_V06/promote.xml Denverton_COMe_CPLD_Denverton_COMe_CPLD.ncd Denverton_COMe_CPLD_Denverton_COMe_CPLD.prf
Design file: denverton_come_cpld_denverton_come_cpld.ncd
Preference file: denverton_come_cpld_denverton_come_cpld.prf
Device,speed: LCMXO2-1200HC,4
Report level: verbose report, limited to 10 items per preference
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Preference Summary
FREQUENCY NET "clk_sys" 66.500000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
Report: 70.432MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY NET "clk_sys" 66.500000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.840ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/RSMRST_N_CNT[1] (from clk_sys +)
Destination: FF Data in power_seq_inst1/RSMRST_N_CNT[17] (to clk_sys +)
Delay: 14.032ns (48.6% logic, 51.4% route), 18 logic levels.
Constraint Details:
14.032ns physical path delay power_seq_inst1/SLICE_83 to SLICE_75 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 0.840ns
Physical Path Details:
Data path power_seq_inst1/SLICE_83 to SLICE_75:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C7B.CLK to R3C7B.Q0 power_seq_inst1/SLICE_83 (from clk_sys)
ROUTE 2 1.604 R3C7B.Q0 to R7C6C.C0 power_seq_inst1/RSMRST_N_CNT[1]
CTOF_DEL --- 0.495 R7C6C.C0 to R7C6C.F0 SLICE_253
ROUTE 1 1.173 R7C6C.F0 to R4C8D.D1 power_seq_inst1/m494_0_a3
CTOF_DEL --- 0.495 R4C8D.D1 to R4C8D.F1 power_seq_inst1/SLICE_322
ROUTE 1 0.436 R4C8D.F1 to R4C8D.C0 power_seq_inst1/N_648_mux
CTOF_DEL --- 0.495 R4C8D.C0 to R4C8D.F0 power_seq_inst1/SLICE_322
ROUTE 1 0.626 R4C8D.F0 to R4C8B.D1 power_seq_inst1/N_664_mux
CTOF_DEL --- 0.495 R4C8B.D1 to R4C8B.F1 power_seq_inst1/SLICE_300
ROUTE 1 0.436 R4C8B.F1 to R4C8B.C0 power_seq_inst1/N_697_mux
CTOF_DEL --- 0.495 R4C8B.C0 to R4C8B.F0 power_seq_inst1/SLICE_300
ROUTE 1 1.079 R4C8B.F0 to R3C9D.C1 power_seq_inst1/N_752_mux
CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 power_seq_inst1/SLICE_288
ROUTE 3 0.445 R3C9D.F1 to R3C9D.C0 power_seq_inst1/N_862_mux
CTOF_DEL --- 0.495 R3C9D.C0 to R3C9D.F0 power_seq_inst1/SLICE_288
ROUTE 19 1.412 R3C9D.F0 to R3C7A.A0 power_seq_inst1/RSMRST_N_CNT
C0TOFCO_DE --- 1.023 R3C7A.A0 to R3C7A.FCO SLICE_84
ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI power_seq_inst1/RSMRST_N_CNT_cry[0]
FCITOFCO_D --- 0.162 R3C7B.FCI to R3C7B.FCO power_seq_inst1/SLICE_83
ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI power_seq_inst1/RSMRST_N_CNT_cry[2]
FCITOFCO_D --- 0.162 R3C7C.FCI to R3C7C.FCO power_seq_inst1/SLICE_82
ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI power_seq_inst1/RSMRST_N_CNT_cry[4]
FCITOFCO_D --- 0.162 R3C7D.FCI to R3C7D.FCO power_seq_inst1/SLICE_81
ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI power_seq_inst1/RSMRST_N_CNT_cry[6]
FCITOFCO_D --- 0.162 R3C8A.FCI to R3C8A.FCO power_seq_inst1/SLICE_80
ROUTE 1 0.000 R3C8A.FCO to R3C8B.FCI power_seq_inst1/RSMRST_N_CNT_cry[8]
FCITOFCO_D --- 0.162 R3C8B.FCI to R3C8B.FCO power_seq_inst1/SLICE_79
ROUTE 1 0.000 R3C8B.FCO to R3C8C.FCI power_seq_inst1/RSMRST_N_CNT_cry[10]
FCITOFCO_D --- 0.162 R3C8C.FCI to R3C8C.FCO power_seq_inst1/SLICE_78
ROUTE 1 0.000 R3C8C.FCO to R3C8D.FCI power_seq_inst1/RSMRST_N_CNT_cry[12]
FCITOFCO_D --- 0.162 R3C8D.FCI to R3C8D.FCO power_seq_inst1/SLICE_77
ROUTE 1 0.000 R3C8D.FCO to R3C9A.FCI power_seq_inst1/RSMRST_N_CNT_cry[14]
FCITOFCO_D --- 0.162 R3C9A.FCI to R3C9A.FCO power_seq_inst1/SLICE_76
ROUTE 1 0.000 R3C9A.FCO to R3C9B.FCI power_seq_inst1/RSMRST_N_CNT_cry[16]
FCITOF0_DE --- 0.585 R3C9B.FCI to R3C9B.F0 SLICE_75
ROUTE 1 0.000 R3C9B.F0 to R3C9B.DI0 power_seq_inst1/RSMRST_N_CNT_s[17] (to clk_sys)
--------
14.032 (48.6% logic, 51.4% route), 18 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to power_seq_inst1/SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C7B.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C9B.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.944ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/RSMRST_N_CNT[1] (from clk_sys +)
Destination: FF Data in power_seq_inst1/RSMRST_N_CNT[16] (to clk_sys +)
Delay: 13.928ns (48.2% logic, 51.8% route), 17 logic levels.
Constraint Details:
13.928ns physical path delay power_seq_inst1/SLICE_83 to power_seq_inst1/SLICE_76 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 0.944ns
Physical Path Details:
Data path power_seq_inst1/SLICE_83 to power_seq_inst1/SLICE_76:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C7B.CLK to R3C7B.Q0 power_seq_inst1/SLICE_83 (from clk_sys)
ROUTE 2 1.604 R3C7B.Q0 to R7C6C.C0 power_seq_inst1/RSMRST_N_CNT[1]
CTOF_DEL --- 0.495 R7C6C.C0 to R7C6C.F0 SLICE_253
ROUTE 1 1.173 R7C6C.F0 to R4C8D.D1 power_seq_inst1/m494_0_a3
CTOF_DEL --- 0.495 R4C8D.D1 to R4C8D.F1 power_seq_inst1/SLICE_322
ROUTE 1 0.436 R4C8D.F1 to R4C8D.C0 power_seq_inst1/N_648_mux
CTOF_DEL --- 0.495 R4C8D.C0 to R4C8D.F0 power_seq_inst1/SLICE_322
ROUTE 1 0.626 R4C8D.F0 to R4C8B.D1 power_seq_inst1/N_664_mux
CTOF_DEL --- 0.495 R4C8B.D1 to R4C8B.F1 power_seq_inst1/SLICE_300
ROUTE 1 0.436 R4C8B.F1 to R4C8B.C0 power_seq_inst1/N_697_mux
CTOF_DEL --- 0.495 R4C8B.C0 to R4C8B.F0 power_seq_inst1/SLICE_300
ROUTE 1 1.079 R4C8B.F0 to R3C9D.C1 power_seq_inst1/N_752_mux
CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 power_seq_inst1/SLICE_288
ROUTE 3 0.445 R3C9D.F1 to R3C9D.C0 power_seq_inst1/N_862_mux
CTOF_DEL --- 0.495 R3C9D.C0 to R3C9D.F0 power_seq_inst1/SLICE_288
ROUTE 19 1.412 R3C9D.F0 to R3C7A.A0 power_seq_inst1/RSMRST_N_CNT
C0TOFCO_DE --- 1.023 R3C7A.A0 to R3C7A.FCO SLICE_84
ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI power_seq_inst1/RSMRST_N_CNT_cry[0]
FCITOFCO_D --- 0.162 R3C7B.FCI to R3C7B.FCO power_seq_inst1/SLICE_83
ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI power_seq_inst1/RSMRST_N_CNT_cry[2]
FCITOFCO_D --- 0.162 R3C7C.FCI to R3C7C.FCO power_seq_inst1/SLICE_82
ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI power_seq_inst1/RSMRST_N_CNT_cry[4]
FCITOFCO_D --- 0.162 R3C7D.FCI to R3C7D.FCO power_seq_inst1/SLICE_81
ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI power_seq_inst1/RSMRST_N_CNT_cry[6]
FCITOFCO_D --- 0.162 R3C8A.FCI to R3C8A.FCO power_seq_inst1/SLICE_80
ROUTE 1 0.000 R3C8A.FCO to R3C8B.FCI power_seq_inst1/RSMRST_N_CNT_cry[8]
FCITOFCO_D --- 0.162 R3C8B.FCI to R3C8B.FCO power_seq_inst1/SLICE_79
ROUTE 1 0.000 R3C8B.FCO to R3C8C.FCI power_seq_inst1/RSMRST_N_CNT_cry[10]
FCITOFCO_D --- 0.162 R3C8C.FCI to R3C8C.FCO power_seq_inst1/SLICE_78
ROUTE 1 0.000 R3C8C.FCO to R3C8D.FCI power_seq_inst1/RSMRST_N_CNT_cry[12]
FCITOFCO_D --- 0.162 R3C8D.FCI to R3C8D.FCO power_seq_inst1/SLICE_77
ROUTE 1 0.000 R3C8D.FCO to R3C9A.FCI power_seq_inst1/RSMRST_N_CNT_cry[14]
FCITOF1_DE --- 0.643 R3C9A.FCI to R3C9A.F1 power_seq_inst1/SLICE_76
ROUTE 1 0.000 R3C9A.F1 to R3C9A.DI1 power_seq_inst1/RSMRST_N_CNT_s[16] (to clk_sys)
--------
13.928 (48.2% logic, 51.8% route), 17 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to power_seq_inst1/SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C7B.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to power_seq_inst1/SLICE_76:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C9A.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.961ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/RSMRST_N_CNT[0] (from clk_sys +)
Destination: FF Data in power_seq_inst1/RSMRST_N_CNT[17] (to clk_sys +)
Delay: 13.911ns (49.0% logic, 51.0% route), 18 logic levels.
Constraint Details:
13.911ns physical path delay SLICE_84 to SLICE_75 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 0.961ns
Physical Path Details:
Data path SLICE_84 to SLICE_75:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C7A.CLK to R3C7A.Q1 SLICE_84 (from clk_sys)
ROUTE 2 1.483 R3C7A.Q1 to R7C6C.D0 power_seq_inst1/RSMRST_N_CNT[0]
CTOF_DEL --- 0.495 R7C6C.D0 to R7C6C.F0 SLICE_253
ROUTE 1 1.173 R7C6C.F0 to R4C8D.D1 power_seq_inst1/m494_0_a3
CTOF_DEL --- 0.495 R4C8D.D1 to R4C8D.F1 power_seq_inst1/SLICE_322
ROUTE 1 0.436 R4C8D.F1 to R4C8D.C0 power_seq_inst1/N_648_mux
CTOF_DEL --- 0.495 R4C8D.C0 to R4C8D.F0 power_seq_inst1/SLICE_322
ROUTE 1 0.626 R4C8D.F0 to R4C8B.D1 power_seq_inst1/N_664_mux
CTOF_DEL --- 0.495 R4C8B.D1 to R4C8B.F1 power_seq_inst1/SLICE_300
ROUTE 1 0.436 R4C8B.F1 to R4C8B.C0 power_seq_inst1/N_697_mux
CTOF_DEL --- 0.495 R4C8B.C0 to R4C8B.F0 power_seq_inst1/SLICE_300
ROUTE 1 1.079 R4C8B.F0 to R3C9D.C1 power_seq_inst1/N_752_mux
CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 power_seq_inst1/SLICE_288
ROUTE 3 0.445 R3C9D.F1 to R3C9D.C0 power_seq_inst1/N_862_mux
CTOF_DEL --- 0.495 R3C9D.C0 to R3C9D.F0 power_seq_inst1/SLICE_288
ROUTE 19 1.412 R3C9D.F0 to R3C7A.A0 power_seq_inst1/RSMRST_N_CNT
C0TOFCO_DE --- 1.023 R3C7A.A0 to R3C7A.FCO SLICE_84
ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI power_seq_inst1/RSMRST_N_CNT_cry[0]
FCITOFCO_D --- 0.162 R3C7B.FCI to R3C7B.FCO power_seq_inst1/SLICE_83
ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI power_seq_inst1/RSMRST_N_CNT_cry[2]
FCITOFCO_D --- 0.162 R3C7C.FCI to R3C7C.FCO power_seq_inst1/SLICE_82
ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI power_seq_inst1/RSMRST_N_CNT_cry[4]
FCITOFCO_D --- 0.162 R3C7D.FCI to R3C7D.FCO power_seq_inst1/SLICE_81
ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI power_seq_inst1/RSMRST_N_CNT_cry[6]
FCITOFCO_D --- 0.162 R3C8A.FCI to R3C8A.FCO power_seq_inst1/SLICE_80
ROUTE 1 0.000 R3C8A.FCO to R3C8B.FCI power_seq_inst1/RSMRST_N_CNT_cry[8]
FCITOFCO_D --- 0.162 R3C8B.FCI to R3C8B.FCO power_seq_inst1/SLICE_79
ROUTE 1 0.000 R3C8B.FCO to R3C8C.FCI power_seq_inst1/RSMRST_N_CNT_cry[10]
FCITOFCO_D --- 0.162 R3C8C.FCI to R3C8C.FCO power_seq_inst1/SLICE_78
ROUTE 1 0.000 R3C8C.FCO to R3C8D.FCI power_seq_inst1/RSMRST_N_CNT_cry[12]
FCITOFCO_D --- 0.162 R3C8D.FCI to R3C8D.FCO power_seq_inst1/SLICE_77
ROUTE 1 0.000 R3C8D.FCO to R3C9A.FCI power_seq_inst1/RSMRST_N_CNT_cry[14]
FCITOFCO_D --- 0.162 R3C9A.FCI to R3C9A.FCO power_seq_inst1/SLICE_76
ROUTE 1 0.000 R3C9A.FCO to R3C9B.FCI power_seq_inst1/RSMRST_N_CNT_cry[16]
FCITOF0_DE --- 0.585 R3C9B.FCI to R3C9B.F0 SLICE_75
ROUTE 1 0.000 R3C9B.F0 to R3C9B.DI0 power_seq_inst1/RSMRST_N_CNT_s[17] (to clk_sys)
--------
13.911 (49.0% logic, 51.0% route), 18 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_84:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C7A.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C9B.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.974ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/RSMRST_N_CNT[1] (from clk_sys +)
Destination: FF Data in power_seq_inst1/RSMRST_N_CNT[17] (to clk_sys +)
Delay: 13.898ns (48.1% logic, 51.9% route), 18 logic levels.
Constraint Details:
13.898ns physical path delay power_seq_inst1/SLICE_83 to SLICE_75 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 0.974ns
Physical Path Details:
Data path power_seq_inst1/SLICE_83 to SLICE_75:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C7B.CLK to R3C7B.Q0 power_seq_inst1/SLICE_83 (from clk_sys)
ROUTE 2 1.604 R3C7B.Q0 to R7C6C.C0 power_seq_inst1/RSMRST_N_CNT[1]
CTOF_DEL --- 0.495 R7C6C.C0 to R7C6C.F0 SLICE_253
ROUTE 1 1.173 R7C6C.F0 to R4C8D.D1 power_seq_inst1/m494_0_a3
CTOF_DEL --- 0.495 R4C8D.D1 to R4C8D.F1 power_seq_inst1/SLICE_322
ROUTE 1 0.436 R4C8D.F1 to R4C8D.C0 power_seq_inst1/N_648_mux
CTOF_DEL --- 0.495 R4C8D.C0 to R4C8D.F0 power_seq_inst1/SLICE_322
ROUTE 1 0.626 R4C8D.F0 to R4C8B.D1 power_seq_inst1/N_664_mux
CTOF_DEL --- 0.495 R4C8B.D1 to R4C8B.F1 power_seq_inst1/SLICE_300
ROUTE 1 0.436 R4C8B.F1 to R4C8B.C0 power_seq_inst1/N_697_mux
CTOF_DEL --- 0.495 R4C8B.C0 to R4C8B.F0 power_seq_inst1/SLICE_300
ROUTE 1 1.079 R4C8B.F0 to R3C9D.C1 power_seq_inst1/N_752_mux
CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 power_seq_inst1/SLICE_288
ROUTE 3 0.445 R3C9D.F1 to R3C9D.C0 power_seq_inst1/N_862_mux
CTOF_DEL --- 0.495 R3C9D.C0 to R3C9D.F0 power_seq_inst1/SLICE_288
ROUTE 19 1.412 R3C9D.F0 to R3C7A.A1 power_seq_inst1/RSMRST_N_CNT
C1TOFCO_DE --- 0.889 R3C7A.A1 to R3C7A.FCO SLICE_84
ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI power_seq_inst1/RSMRST_N_CNT_cry[0]
FCITOFCO_D --- 0.162 R3C7B.FCI to R3C7B.FCO power_seq_inst1/SLICE_83
ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI power_seq_inst1/RSMRST_N_CNT_cry[2]
FCITOFCO_D --- 0.162 R3C7C.FCI to R3C7C.FCO power_seq_inst1/SLICE_82
ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI power_seq_inst1/RSMRST_N_CNT_cry[4]
FCITOFCO_D --- 0.162 R3C7D.FCI to R3C7D.FCO power_seq_inst1/SLICE_81
ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI power_seq_inst1/RSMRST_N_CNT_cry[6]
FCITOFCO_D --- 0.162 R3C8A.FCI to R3C8A.FCO power_seq_inst1/SLICE_80
ROUTE 1 0.000 R3C8A.FCO to R3C8B.FCI power_seq_inst1/RSMRST_N_CNT_cry[8]
FCITOFCO_D --- 0.162 R3C8B.FCI to R3C8B.FCO power_seq_inst1/SLICE_79
ROUTE 1 0.000 R3C8B.FCO to R3C8C.FCI power_seq_inst1/RSMRST_N_CNT_cry[10]
FCITOFCO_D --- 0.162 R3C8C.FCI to R3C8C.FCO power_seq_inst1/SLICE_78
ROUTE 1 0.000 R3C8C.FCO to R3C8D.FCI power_seq_inst1/RSMRST_N_CNT_cry[12]
FCITOFCO_D --- 0.162 R3C8D.FCI to R3C8D.FCO power_seq_inst1/SLICE_77
ROUTE 1 0.000 R3C8D.FCO to R3C9A.FCI power_seq_inst1/RSMRST_N_CNT_cry[14]
FCITOFCO_D --- 0.162 R3C9A.FCI to R3C9A.FCO power_seq_inst1/SLICE_76
ROUTE 1 0.000 R3C9A.FCO to R3C9B.FCI power_seq_inst1/RSMRST_N_CNT_cry[16]
FCITOF0_DE --- 0.585 R3C9B.FCI to R3C9B.F0 SLICE_75
ROUTE 1 0.000 R3C9B.F0 to R3C9B.DI0 power_seq_inst1/RSMRST_N_CNT_s[17] (to clk_sys)
--------
13.898 (48.1% logic, 51.9% route), 18 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to power_seq_inst1/SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C7B.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C9B.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.002ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/RSMRST_N_CNT[1] (from clk_sys +)
Destination: FF Data in power_seq_inst1/RSMRST_N_CNT[17] (to clk_sys +)
Delay: 13.870ns (48.0% logic, 52.0% route), 17 logic levels.
Constraint Details:
13.870ns physical path delay power_seq_inst1/SLICE_83 to SLICE_75 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 1.002ns
Physical Path Details:
Data path power_seq_inst1/SLICE_83 to SLICE_75:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C7B.CLK to R3C7B.Q0 power_seq_inst1/SLICE_83 (from clk_sys)
ROUTE 2 1.604 R3C7B.Q0 to R7C6C.C0 power_seq_inst1/RSMRST_N_CNT[1]
CTOF_DEL --- 0.495 R7C6C.C0 to R7C6C.F0 SLICE_253
ROUTE 1 1.173 R7C6C.F0 to R4C8D.D1 power_seq_inst1/m494_0_a3
CTOF_DEL --- 0.495 R4C8D.D1 to R4C8D.F1 power_seq_inst1/SLICE_322
ROUTE 1 0.436 R4C8D.F1 to R4C8D.C0 power_seq_inst1/N_648_mux
CTOF_DEL --- 0.495 R4C8D.C0 to R4C8D.F0 power_seq_inst1/SLICE_322
ROUTE 1 0.626 R4C8D.F0 to R4C8B.D1 power_seq_inst1/N_664_mux
CTOF_DEL --- 0.495 R4C8B.D1 to R4C8B.F1 power_seq_inst1/SLICE_300
ROUTE 1 0.436 R4C8B.F1 to R4C8B.C0 power_seq_inst1/N_697_mux
CTOF_DEL --- 0.495 R4C8B.C0 to R4C8B.F0 power_seq_inst1/SLICE_300
ROUTE 1 1.079 R4C8B.F0 to R3C9D.C1 power_seq_inst1/N_752_mux
CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 power_seq_inst1/SLICE_288
ROUTE 3 0.445 R3C9D.F1 to R3C9D.C0 power_seq_inst1/N_862_mux
CTOF_DEL --- 0.495 R3C9D.C0 to R3C9D.F0 power_seq_inst1/SLICE_288
ROUTE 19 1.412 R3C9D.F0 to R3C7B.A0 power_seq_inst1/RSMRST_N_CNT
C0TOFCO_DE --- 1.023 R3C7B.A0 to R3C7B.FCO power_seq_inst1/SLICE_83
ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI power_seq_inst1/RSMRST_N_CNT_cry[2]
FCITOFCO_D --- 0.162 R3C7C.FCI to R3C7C.FCO power_seq_inst1/SLICE_82
ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI power_seq_inst1/RSMRST_N_CNT_cry[4]
FCITOFCO_D --- 0.162 R3C7D.FCI to R3C7D.FCO power_seq_inst1/SLICE_81
ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI power_seq_inst1/RSMRST_N_CNT_cry[6]
FCITOFCO_D --- 0.162 R3C8A.FCI to R3C8A.FCO power_seq_inst1/SLICE_80
ROUTE 1 0.000 R3C8A.FCO to R3C8B.FCI power_seq_inst1/RSMRST_N_CNT_cry[8]
FCITOFCO_D --- 0.162 R3C8B.FCI to R3C8B.FCO power_seq_inst1/SLICE_79
ROUTE 1 0.000 R3C8B.FCO to R3C8C.FCI power_seq_inst1/RSMRST_N_CNT_cry[10]
FCITOFCO_D --- 0.162 R3C8C.FCI to R3C8C.FCO power_seq_inst1/SLICE_78
ROUTE 1 0.000 R3C8C.FCO to R3C8D.FCI power_seq_inst1/RSMRST_N_CNT_cry[12]
FCITOFCO_D --- 0.162 R3C8D.FCI to R3C8D.FCO power_seq_inst1/SLICE_77
ROUTE 1 0.000 R3C8D.FCO to R3C9A.FCI power_seq_inst1/RSMRST_N_CNT_cry[14]
FCITOFCO_D --- 0.162 R3C9A.FCI to R3C9A.FCO power_seq_inst1/SLICE_76
ROUTE 1 0.000 R3C9A.FCO to R3C9B.FCI power_seq_inst1/RSMRST_N_CNT_cry[16]
FCITOF0_DE --- 0.585 R3C9B.FCI to R3C9B.F0 SLICE_75
ROUTE 1 0.000 R3C9B.F0 to R3C9B.DI0 power_seq_inst1/RSMRST_N_CNT_s[17] (to clk_sys)
--------
13.870 (48.0% logic, 52.0% route), 17 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to power_seq_inst1/SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C7B.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C9B.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.002ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/RSMRST_N_CNT[1] (from clk_sys +)
Destination: FF Data in power_seq_inst1/RSMRST_N_CNT[15] (to clk_sys +)
Delay: 13.870ns (48.0% logic, 52.0% route), 17 logic levels.
Constraint Details:
13.870ns physical path delay power_seq_inst1/SLICE_83 to power_seq_inst1/SLICE_76 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 1.002ns
Physical Path Details:
Data path power_seq_inst1/SLICE_83 to power_seq_inst1/SLICE_76:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C7B.CLK to R3C7B.Q0 power_seq_inst1/SLICE_83 (from clk_sys)
ROUTE 2 1.604 R3C7B.Q0 to R7C6C.C0 power_seq_inst1/RSMRST_N_CNT[1]
CTOF_DEL --- 0.495 R7C6C.C0 to R7C6C.F0 SLICE_253
ROUTE 1 1.173 R7C6C.F0 to R4C8D.D1 power_seq_inst1/m494_0_a3
CTOF_DEL --- 0.495 R4C8D.D1 to R4C8D.F1 power_seq_inst1/SLICE_322
ROUTE 1 0.436 R4C8D.F1 to R4C8D.C0 power_seq_inst1/N_648_mux
CTOF_DEL --- 0.495 R4C8D.C0 to R4C8D.F0 power_seq_inst1/SLICE_322
ROUTE 1 0.626 R4C8D.F0 to R4C8B.D1 power_seq_inst1/N_664_mux
CTOF_DEL --- 0.495 R4C8B.D1 to R4C8B.F1 power_seq_inst1/SLICE_300
ROUTE 1 0.436 R4C8B.F1 to R4C8B.C0 power_seq_inst1/N_697_mux
CTOF_DEL --- 0.495 R4C8B.C0 to R4C8B.F0 power_seq_inst1/SLICE_300
ROUTE 1 1.079 R4C8B.F0 to R3C9D.C1 power_seq_inst1/N_752_mux
CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 power_seq_inst1/SLICE_288
ROUTE 3 0.445 R3C9D.F1 to R3C9D.C0 power_seq_inst1/N_862_mux
CTOF_DEL --- 0.495 R3C9D.C0 to R3C9D.F0 power_seq_inst1/SLICE_288
ROUTE 19 1.412 R3C9D.F0 to R3C7A.A0 power_seq_inst1/RSMRST_N_CNT
C0TOFCO_DE --- 1.023 R3C7A.A0 to R3C7A.FCO SLICE_84
ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI power_seq_inst1/RSMRST_N_CNT_cry[0]
FCITOFCO_D --- 0.162 R3C7B.FCI to R3C7B.FCO power_seq_inst1/SLICE_83
ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI power_seq_inst1/RSMRST_N_CNT_cry[2]
FCITOFCO_D --- 0.162 R3C7C.FCI to R3C7C.FCO power_seq_inst1/SLICE_82
ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI power_seq_inst1/RSMRST_N_CNT_cry[4]
FCITOFCO_D --- 0.162 R3C7D.FCI to R3C7D.FCO power_seq_inst1/SLICE_81
ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI power_seq_inst1/RSMRST_N_CNT_cry[6]
FCITOFCO_D --- 0.162 R3C8A.FCI to R3C8A.FCO power_seq_inst1/SLICE_80
ROUTE 1 0.000 R3C8A.FCO to R3C8B.FCI power_seq_inst1/RSMRST_N_CNT_cry[8]
FCITOFCO_D --- 0.162 R3C8B.FCI to R3C8B.FCO power_seq_inst1/SLICE_79
ROUTE 1 0.000 R3C8B.FCO to R3C8C.FCI power_seq_inst1/RSMRST_N_CNT_cry[10]
FCITOFCO_D --- 0.162 R3C8C.FCI to R3C8C.FCO power_seq_inst1/SLICE_78
ROUTE 1 0.000 R3C8C.FCO to R3C8D.FCI power_seq_inst1/RSMRST_N_CNT_cry[12]
FCITOFCO_D --- 0.162 R3C8D.FCI to R3C8D.FCO power_seq_inst1/SLICE_77
ROUTE 1 0.000 R3C8D.FCO to R3C9A.FCI power_seq_inst1/RSMRST_N_CNT_cry[14]
FCITOF0_DE --- 0.585 R3C9A.FCI to R3C9A.F0 power_seq_inst1/SLICE_76
ROUTE 1 0.000 R3C9A.F0 to R3C9A.DI0 power_seq_inst1/RSMRST_N_CNT_s[15] (to clk_sys)
--------
13.870 (48.0% logic, 52.0% route), 17 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to power_seq_inst1/SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C7B.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to power_seq_inst1/SLICE_76:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C9A.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.065ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/RSMRST_N_CNT[0] (from clk_sys +)
Destination: FF Data in power_seq_inst1/RSMRST_N_CNT[16] (to clk_sys +)
Delay: 13.807ns (48.6% logic, 51.4% route), 17 logic levels.
Constraint Details:
13.807ns physical path delay SLICE_84 to power_seq_inst1/SLICE_76 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 1.065ns
Physical Path Details:
Data path SLICE_84 to power_seq_inst1/SLICE_76:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C7A.CLK to R3C7A.Q1 SLICE_84 (from clk_sys)
ROUTE 2 1.483 R3C7A.Q1 to R7C6C.D0 power_seq_inst1/RSMRST_N_CNT[0]
CTOF_DEL --- 0.495 R7C6C.D0 to R7C6C.F0 SLICE_253
ROUTE 1 1.173 R7C6C.F0 to R4C8D.D1 power_seq_inst1/m494_0_a3
CTOF_DEL --- 0.495 R4C8D.D1 to R4C8D.F1 power_seq_inst1/SLICE_322
ROUTE 1 0.436 R4C8D.F1 to R4C8D.C0 power_seq_inst1/N_648_mux
CTOF_DEL --- 0.495 R4C8D.C0 to R4C8D.F0 power_seq_inst1/SLICE_322
ROUTE 1 0.626 R4C8D.F0 to R4C8B.D1 power_seq_inst1/N_664_mux
CTOF_DEL --- 0.495 R4C8B.D1 to R4C8B.F1 power_seq_inst1/SLICE_300
ROUTE 1 0.436 R4C8B.F1 to R4C8B.C0 power_seq_inst1/N_697_mux
CTOF_DEL --- 0.495 R4C8B.C0 to R4C8B.F0 power_seq_inst1/SLICE_300
ROUTE 1 1.079 R4C8B.F0 to R3C9D.C1 power_seq_inst1/N_752_mux
CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 power_seq_inst1/SLICE_288
ROUTE 3 0.445 R3C9D.F1 to R3C9D.C0 power_seq_inst1/N_862_mux
CTOF_DEL --- 0.495 R3C9D.C0 to R3C9D.F0 power_seq_inst1/SLICE_288
ROUTE 19 1.412 R3C9D.F0 to R3C7A.A0 power_seq_inst1/RSMRST_N_CNT
C0TOFCO_DE --- 1.023 R3C7A.A0 to R3C7A.FCO SLICE_84
ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI power_seq_inst1/RSMRST_N_CNT_cry[0]
FCITOFCO_D --- 0.162 R3C7B.FCI to R3C7B.FCO power_seq_inst1/SLICE_83
ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI power_seq_inst1/RSMRST_N_CNT_cry[2]
FCITOFCO_D --- 0.162 R3C7C.FCI to R3C7C.FCO power_seq_inst1/SLICE_82
ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI power_seq_inst1/RSMRST_N_CNT_cry[4]
FCITOFCO_D --- 0.162 R3C7D.FCI to R3C7D.FCO power_seq_inst1/SLICE_81
ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI power_seq_inst1/RSMRST_N_CNT_cry[6]
FCITOFCO_D --- 0.162 R3C8A.FCI to R3C8A.FCO power_seq_inst1/SLICE_80
ROUTE 1 0.000 R3C8A.FCO to R3C8B.FCI power_seq_inst1/RSMRST_N_CNT_cry[8]
FCITOFCO_D --- 0.162 R3C8B.FCI to R3C8B.FCO power_seq_inst1/SLICE_79
ROUTE 1 0.000 R3C8B.FCO to R3C8C.FCI power_seq_inst1/RSMRST_N_CNT_cry[10]
FCITOFCO_D --- 0.162 R3C8C.FCI to R3C8C.FCO power_seq_inst1/SLICE_78
ROUTE 1 0.000 R3C8C.FCO to R3C8D.FCI power_seq_inst1/RSMRST_N_CNT_cry[12]
FCITOFCO_D --- 0.162 R3C8D.FCI to R3C8D.FCO power_seq_inst1/SLICE_77
ROUTE 1 0.000 R3C8D.FCO to R3C9A.FCI power_seq_inst1/RSMRST_N_CNT_cry[14]
FCITOF1_DE --- 0.643 R3C9A.FCI to R3C9A.F1 power_seq_inst1/SLICE_76
ROUTE 1 0.000 R3C9A.F1 to R3C9A.DI1 power_seq_inst1/RSMRST_N_CNT_s[16] (to clk_sys)
--------
13.807 (48.6% logic, 51.4% route), 17 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_84:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C7A.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to power_seq_inst1/SLICE_76:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C9A.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.078ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/RSMRST_N_CNT[1] (from clk_sys +)
Destination: FF Data in power_seq_inst1/RSMRST_N_CNT[16] (to clk_sys +)
Delay: 13.794ns (47.7% logic, 52.3% route), 17 logic levels.
Constraint Details:
13.794ns physical path delay power_seq_inst1/SLICE_83 to power_seq_inst1/SLICE_76 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 1.078ns
Physical Path Details:
Data path power_seq_inst1/SLICE_83 to power_seq_inst1/SLICE_76:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C7B.CLK to R3C7B.Q0 power_seq_inst1/SLICE_83 (from clk_sys)
ROUTE 2 1.604 R3C7B.Q0 to R7C6C.C0 power_seq_inst1/RSMRST_N_CNT[1]
CTOF_DEL --- 0.495 R7C6C.C0 to R7C6C.F0 SLICE_253
ROUTE 1 1.173 R7C6C.F0 to R4C8D.D1 power_seq_inst1/m494_0_a3
CTOF_DEL --- 0.495 R4C8D.D1 to R4C8D.F1 power_seq_inst1/SLICE_322
ROUTE 1 0.436 R4C8D.F1 to R4C8D.C0 power_seq_inst1/N_648_mux
CTOF_DEL --- 0.495 R4C8D.C0 to R4C8D.F0 power_seq_inst1/SLICE_322
ROUTE 1 0.626 R4C8D.F0 to R4C8B.D1 power_seq_inst1/N_664_mux
CTOF_DEL --- 0.495 R4C8B.D1 to R4C8B.F1 power_seq_inst1/SLICE_300
ROUTE 1 0.436 R4C8B.F1 to R4C8B.C0 power_seq_inst1/N_697_mux
CTOF_DEL --- 0.495 R4C8B.C0 to R4C8B.F0 power_seq_inst1/SLICE_300
ROUTE 1 1.079 R4C8B.F0 to R3C9D.C1 power_seq_inst1/N_752_mux
CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 power_seq_inst1/SLICE_288
ROUTE 3 0.445 R3C9D.F1 to R3C9D.C0 power_seq_inst1/N_862_mux
CTOF_DEL --- 0.495 R3C9D.C0 to R3C9D.F0 power_seq_inst1/SLICE_288
ROUTE 19 1.412 R3C9D.F0 to R3C7A.A1 power_seq_inst1/RSMRST_N_CNT
C1TOFCO_DE --- 0.889 R3C7A.A1 to R3C7A.FCO SLICE_84
ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI power_seq_inst1/RSMRST_N_CNT_cry[0]
FCITOFCO_D --- 0.162 R3C7B.FCI to R3C7B.FCO power_seq_inst1/SLICE_83
ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI power_seq_inst1/RSMRST_N_CNT_cry[2]
FCITOFCO_D --- 0.162 R3C7C.FCI to R3C7C.FCO power_seq_inst1/SLICE_82
ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI power_seq_inst1/RSMRST_N_CNT_cry[4]
FCITOFCO_D --- 0.162 R3C7D.FCI to R3C7D.FCO power_seq_inst1/SLICE_81
ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI power_seq_inst1/RSMRST_N_CNT_cry[6]
FCITOFCO_D --- 0.162 R3C8A.FCI to R3C8A.FCO power_seq_inst1/SLICE_80
ROUTE 1 0.000 R3C8A.FCO to R3C8B.FCI power_seq_inst1/RSMRST_N_CNT_cry[8]
FCITOFCO_D --- 0.162 R3C8B.FCI to R3C8B.FCO power_seq_inst1/SLICE_79
ROUTE 1 0.000 R3C8B.FCO to R3C8C.FCI power_seq_inst1/RSMRST_N_CNT_cry[10]
FCITOFCO_D --- 0.162 R3C8C.FCI to R3C8C.FCO power_seq_inst1/SLICE_78
ROUTE 1 0.000 R3C8C.FCO to R3C8D.FCI power_seq_inst1/RSMRST_N_CNT_cry[12]
FCITOFCO_D --- 0.162 R3C8D.FCI to R3C8D.FCO power_seq_inst1/SLICE_77
ROUTE 1 0.000 R3C8D.FCO to R3C9A.FCI power_seq_inst1/RSMRST_N_CNT_cry[14]
FCITOF1_DE --- 0.643 R3C9A.FCI to R3C9A.F1 power_seq_inst1/SLICE_76
ROUTE 1 0.000 R3C9A.F1 to R3C9A.DI1 power_seq_inst1/RSMRST_N_CNT_s[16] (to clk_sys)
--------
13.794 (47.7% logic, 52.3% route), 17 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to power_seq_inst1/SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C7B.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to power_seq_inst1/SLICE_76:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C9A.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.095ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/RSMRST_N_CNT[0] (from clk_sys +)
Destination: FF Data in power_seq_inst1/RSMRST_N_CNT[17] (to clk_sys +)
Delay: 13.777ns (48.5% logic, 51.5% route), 18 logic levels.
Constraint Details:
13.777ns physical path delay SLICE_84 to SLICE_75 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 1.095ns
Physical Path Details:
Data path SLICE_84 to SLICE_75:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C7A.CLK to R3C7A.Q1 SLICE_84 (from clk_sys)
ROUTE 2 1.483 R3C7A.Q1 to R7C6C.D0 power_seq_inst1/RSMRST_N_CNT[0]
CTOF_DEL --- 0.495 R7C6C.D0 to R7C6C.F0 SLICE_253
ROUTE 1 1.173 R7C6C.F0 to R4C8D.D1 power_seq_inst1/m494_0_a3
CTOF_DEL --- 0.495 R4C8D.D1 to R4C8D.F1 power_seq_inst1/SLICE_322
ROUTE 1 0.436 R4C8D.F1 to R4C8D.C0 power_seq_inst1/N_648_mux
CTOF_DEL --- 0.495 R4C8D.C0 to R4C8D.F0 power_seq_inst1/SLICE_322
ROUTE 1 0.626 R4C8D.F0 to R4C8B.D1 power_seq_inst1/N_664_mux
CTOF_DEL --- 0.495 R4C8B.D1 to R4C8B.F1 power_seq_inst1/SLICE_300
ROUTE 1 0.436 R4C8B.F1 to R4C8B.C0 power_seq_inst1/N_697_mux
CTOF_DEL --- 0.495 R4C8B.C0 to R4C8B.F0 power_seq_inst1/SLICE_300
ROUTE 1 1.079 R4C8B.F0 to R3C9D.C1 power_seq_inst1/N_752_mux
CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 power_seq_inst1/SLICE_288
ROUTE 3 0.445 R3C9D.F1 to R3C9D.C0 power_seq_inst1/N_862_mux
CTOF_DEL --- 0.495 R3C9D.C0 to R3C9D.F0 power_seq_inst1/SLICE_288
ROUTE 19 1.412 R3C9D.F0 to R3C7A.A1 power_seq_inst1/RSMRST_N_CNT
C1TOFCO_DE --- 0.889 R3C7A.A1 to R3C7A.FCO SLICE_84
ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI power_seq_inst1/RSMRST_N_CNT_cry[0]
FCITOFCO_D --- 0.162 R3C7B.FCI to R3C7B.FCO power_seq_inst1/SLICE_83
ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI power_seq_inst1/RSMRST_N_CNT_cry[2]
FCITOFCO_D --- 0.162 R3C7C.FCI to R3C7C.FCO power_seq_inst1/SLICE_82
ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI power_seq_inst1/RSMRST_N_CNT_cry[4]
FCITOFCO_D --- 0.162 R3C7D.FCI to R3C7D.FCO power_seq_inst1/SLICE_81
ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI power_seq_inst1/RSMRST_N_CNT_cry[6]
FCITOFCO_D --- 0.162 R3C8A.FCI to R3C8A.FCO power_seq_inst1/SLICE_80
ROUTE 1 0.000 R3C8A.FCO to R3C8B.FCI power_seq_inst1/RSMRST_N_CNT_cry[8]
FCITOFCO_D --- 0.162 R3C8B.FCI to R3C8B.FCO power_seq_inst1/SLICE_79
ROUTE 1 0.000 R3C8B.FCO to R3C8C.FCI power_seq_inst1/RSMRST_N_CNT_cry[10]
FCITOFCO_D --- 0.162 R3C8C.FCI to R3C8C.FCO power_seq_inst1/SLICE_78
ROUTE 1 0.000 R3C8C.FCO to R3C8D.FCI power_seq_inst1/RSMRST_N_CNT_cry[12]
FCITOFCO_D --- 0.162 R3C8D.FCI to R3C8D.FCO power_seq_inst1/SLICE_77
ROUTE 1 0.000 R3C8D.FCO to R3C9A.FCI power_seq_inst1/RSMRST_N_CNT_cry[14]
FCITOFCO_D --- 0.162 R3C9A.FCI to R3C9A.FCO power_seq_inst1/SLICE_76
ROUTE 1 0.000 R3C9A.FCO to R3C9B.FCI power_seq_inst1/RSMRST_N_CNT_cry[16]
FCITOF0_DE --- 0.585 R3C9B.FCI to R3C9B.F0 SLICE_75
ROUTE 1 0.000 R3C9B.F0 to R3C9B.DI0 power_seq_inst1/RSMRST_N_CNT_s[17] (to clk_sys)
--------
13.777 (48.5% logic, 51.5% route), 18 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_84:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C7A.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C9B.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.106ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/RSMRST_N_CNT[1] (from clk_sys +)
Destination: FF Data in power_seq_inst1/RSMRST_N_CNT[16] (to clk_sys +)
Delay: 13.766ns (47.6% logic, 52.4% route), 16 logic levels.
Constraint Details:
13.766ns physical path delay power_seq_inst1/SLICE_83 to power_seq_inst1/SLICE_76 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 1.106ns
Physical Path Details:
Data path power_seq_inst1/SLICE_83 to power_seq_inst1/SLICE_76:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C7B.CLK to R3C7B.Q0 power_seq_inst1/SLICE_83 (from clk_sys)
ROUTE 2 1.604 R3C7B.Q0 to R7C6C.C0 power_seq_inst1/RSMRST_N_CNT[1]
CTOF_DEL --- 0.495 R7C6C.C0 to R7C6C.F0 SLICE_253
ROUTE 1 1.173 R7C6C.F0 to R4C8D.D1 power_seq_inst1/m494_0_a3
CTOF_DEL --- 0.495 R4C8D.D1 to R4C8D.F1 power_seq_inst1/SLICE_322
ROUTE 1 0.436 R4C8D.F1 to R4C8D.C0 power_seq_inst1/N_648_mux
CTOF_DEL --- 0.495 R4C8D.C0 to R4C8D.F0 power_seq_inst1/SLICE_322
ROUTE 1 0.626 R4C8D.F0 to R4C8B.D1 power_seq_inst1/N_664_mux
CTOF_DEL --- 0.495 R4C8B.D1 to R4C8B.F1 power_seq_inst1/SLICE_300
ROUTE 1 0.436 R4C8B.F1 to R4C8B.C0 power_seq_inst1/N_697_mux
CTOF_DEL --- 0.495 R4C8B.C0 to R4C8B.F0 power_seq_inst1/SLICE_300
ROUTE 1 1.079 R4C8B.F0 to R3C9D.C1 power_seq_inst1/N_752_mux
CTOF_DEL --- 0.495 R3C9D.C1 to R3C9D.F1 power_seq_inst1/SLICE_288
ROUTE 3 0.445 R3C9D.F1 to R3C9D.C0 power_seq_inst1/N_862_mux
CTOF_DEL --- 0.495 R3C9D.C0 to R3C9D.F0 power_seq_inst1/SLICE_288
ROUTE 19 1.412 R3C9D.F0 to R3C7B.A0 power_seq_inst1/RSMRST_N_CNT
C0TOFCO_DE --- 1.023 R3C7B.A0 to R3C7B.FCO power_seq_inst1/SLICE_83
ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI power_seq_inst1/RSMRST_N_CNT_cry[2]
FCITOFCO_D --- 0.162 R3C7C.FCI to R3C7C.FCO power_seq_inst1/SLICE_82
ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI power_seq_inst1/RSMRST_N_CNT_cry[4]
FCITOFCO_D --- 0.162 R3C7D.FCI to R3C7D.FCO power_seq_inst1/SLICE_81
ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI power_seq_inst1/RSMRST_N_CNT_cry[6]
FCITOFCO_D --- 0.162 R3C8A.FCI to R3C8A.FCO power_seq_inst1/SLICE_80
ROUTE 1 0.000 R3C8A.FCO to R3C8B.FCI power_seq_inst1/RSMRST_N_CNT_cry[8]
FCITOFCO_D --- 0.162 R3C8B.FCI to R3C8B.FCO power_seq_inst1/SLICE_79
ROUTE 1 0.000 R3C8B.FCO to R3C8C.FCI power_seq_inst1/RSMRST_N_CNT_cry[10]
FCITOFCO_D --- 0.162 R3C8C.FCI to R3C8C.FCO power_seq_inst1/SLICE_78
ROUTE 1 0.000 R3C8C.FCO to R3C8D.FCI power_seq_inst1/RSMRST_N_CNT_cry[12]
FCITOFCO_D --- 0.162 R3C8D.FCI to R3C8D.FCO power_seq_inst1/SLICE_77
ROUTE 1 0.000 R3C8D.FCO to R3C9A.FCI power_seq_inst1/RSMRST_N_CNT_cry[14]
FCITOF1_DE --- 0.643 R3C9A.FCI to R3C9A.F1 power_seq_inst1/SLICE_76
ROUTE 1 0.000 R3C9A.F1 to R3C9A.DI1 power_seq_inst1/RSMRST_N_CNT_s[16] (to clk_sys)
--------
13.766 (47.6% logic, 52.4% route), 16 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to power_seq_inst1/SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C7B.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to power_seq_inst1/SLICE_76:
Name Fanout Delay (ns) Site Resource
ROUTE 248 3.541 OSC.OSC to R3C9A.CLK clk_sys
--------
3.541 (0.0% logic, 100.0% route), 0 logic levels.
Report: 70.432MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_sys" 66.500000 MHz ; | 66.500 MHz| 70.432 MHz| 18
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: LPC_CLK_c Source: LPC_CLK.PAD Loads: 27
No transfer within this clock domain is found
Clock Domain: clk_sys Source: OSCH_inst.OSC Loads: 248
Covered under: FREQUENCY NET "clk_sys" 66.500000 MHz ;
Data transfers from:
Clock Domain: LPC_CLK_c Source: LPC_CLK.PAD
Not reported because source and destination domains are unrelated.
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 43128 paths, 1 nets, and 2379 connections (80.92% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.10.3.144
Sat Apr 04 10:50:13 2020
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Denverton_COMe_CPLD_Denverton_COMe_CPLD.twr -gui -msgset E:/ydc/cpld/Questone 2/2.PLD/Data/20190120-debug/cpld/come_debug/COMe_V06/promote.xml Denverton_COMe_CPLD_Denverton_COMe_CPLD.ncd Denverton_COMe_CPLD_Denverton_COMe_CPLD.prf
Design file: denverton_come_cpld_denverton_come_cpld.ncd
Preference file: denverton_come_cpld_denverton_come_cpld.prf
Device,speed: LCMXO2-1200HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "clk_sys" 66.500000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "clk_sys" 66.500000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_lpc_rd_en_dly[0] (from clk_sys +)
Destination: FF Data in s_lpc_rd_en_dly[1] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_249 to SLICE_249 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_249 to SLICE_249:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R10C8C.CLK to R10C8C.Q0 SLICE_249 (from clk_sys)
ROUTE 1 0.152 R10C8C.Q0 to R10C8C.M1 s_lpc_rd_en_dly[0] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_249:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R10C8C.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_249:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R10C8C.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/s_xp1r05v_pgood[1] (from clk_sys +)
Destination: FF Data in power_seq_inst1/s_xp1r05v_pgood[2] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay power_seq_inst1/SLICE_335 to power_seq_inst1/SLICE_335 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path power_seq_inst1/SLICE_335 to power_seq_inst1/SLICE_335:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C19C.CLK to R4C19C.Q0 power_seq_inst1/SLICE_335 (from clk_sys)
ROUTE 1 0.152 R4C19C.Q0 to R4C19C.M1 power_seq_inst1/s_xp1r05v_pgood[1] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to power_seq_inst1/SLICE_335:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R4C19C.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to power_seq_inst1/SLICE_335:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R4C19C.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/s_xp1r8v_pgood[1] (from clk_sys +)
Destination: FF Data in power_seq_inst1/s_xp1r8v_pgood[2] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay power_seq_inst1/SLICE_261 to power_seq_inst1/SLICE_261 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path power_seq_inst1/SLICE_261 to power_seq_inst1/SLICE_261:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R9C18A.CLK to R9C18A.Q0 power_seq_inst1/SLICE_261 (from clk_sys)
ROUTE 1 0.152 R9C18A.Q0 to R9C18A.M1 power_seq_inst1/s_xp1r8v_pgood[1] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to power_seq_inst1/SLICE_261:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R9C18A.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to power_seq_inst1/SLICE_261:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R9C18A.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/s_xp2r5v_pgood[1] (from clk_sys +)
Destination: FF Data in power_seq_inst1/s_xp2r5v_pgood[2] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay power_seq_inst1/SLICE_373 to power_seq_inst1/SLICE_373 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path power_seq_inst1/SLICE_373 to power_seq_inst1/SLICE_373:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R8C18B.CLK to R8C18B.Q0 power_seq_inst1/SLICE_373 (from clk_sys)
ROUTE 1 0.152 R8C18B.Q0 to R8C18B.M1 power_seq_inst1/s_xp2r5v_pgood[1] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to power_seq_inst1/SLICE_373:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R8C18B.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to power_seq_inst1/SLICE_373:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R8C18B.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/s_xp1r24v_pgood[1] (from clk_sys +)
Destination: FF Data in power_seq_inst1/s_xp1r24v_pgood[2] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay power_seq_inst1/SLICE_325 to power_seq_inst1/SLICE_325 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path power_seq_inst1/SLICE_325 to power_seq_inst1/SLICE_325:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C18C.CLK to R4C18C.Q0 power_seq_inst1/SLICE_325 (from clk_sys)
ROUTE 1 0.152 R4C18C.Q0 to R4C18C.M1 power_seq_inst1/s_xp1r24v_pgood[1] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to power_seq_inst1/SLICE_325:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R4C18C.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to power_seq_inst1/SLICE_325:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R4C18C.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/s_xp0r6v_pgood[1] (from clk_sys +)
Destination: FF Data in power_seq_inst1/s_xp0r6v_pgood[2] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay power_seq_inst1/SLICE_302 to power_seq_inst1/SLICE_302 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path power_seq_inst1/SLICE_302 to power_seq_inst1/SLICE_302:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C18D.CLK to R4C18D.Q0 power_seq_inst1/SLICE_302 (from clk_sys)
ROUTE 1 0.152 R4C18D.Q0 to R4C18D.M1 power_seq_inst1/s_xp0r6v_pgood[1] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to power_seq_inst1/SLICE_302:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R4C18D.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to power_seq_inst1/SLICE_302:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R4C18D.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/s_vccp_pgood[1] (from clk_sys +)
Destination: FF Data in power_seq_inst1/s_vccp_pgood[2] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay power_seq_inst1/SLICE_326 to power_seq_inst1/SLICE_326 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path power_seq_inst1/SLICE_326 to power_seq_inst1/SLICE_326:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C16D.CLK to R7C16D.Q0 power_seq_inst1/SLICE_326 (from clk_sys)
ROUTE 1 0.152 R7C16D.Q0 to R7C16D.M1 power_seq_inst1/s_vccp_pgood[1] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to power_seq_inst1/SLICE_326:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R7C16D.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to power_seq_inst1/SLICE_326:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R7C16D.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/s_vccramp_pgood[1] (from clk_sys +)
Destination: FF Data in power_seq_inst1/s_vccramp_pgood[2] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay power_seq_inst1/SLICE_295 to power_seq_inst1/SLICE_295 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path power_seq_inst1/SLICE_295 to power_seq_inst1/SLICE_295:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C16C.CLK to R4C16C.Q0 power_seq_inst1/SLICE_295 (from clk_sys)
ROUTE 1 0.152 R4C16C.Q0 to R4C16C.M1 power_seq_inst1/s_vccramp_pgood[1] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to power_seq_inst1/SLICE_295:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R4C16C.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to power_seq_inst1/SLICE_295:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R4C16C.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/s_vddqp_pgood[1] (from clk_sys +)
Destination: FF Data in power_seq_inst1/s_vddqp_pgood[2] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay power_seq_inst1/SLICE_337 to power_seq_inst1/SLICE_337 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path power_seq_inst1/SLICE_337 to power_seq_inst1/SLICE_337:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C17C.CLK to R3C17C.Q0 power_seq_inst1/SLICE_337 (from clk_sys)
ROUTE 1 0.152 R3C17C.Q0 to R3C17C.M1 power_seq_inst1/s_vddqp_pgood[1] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to power_seq_inst1/SLICE_337:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R3C17C.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to power_seq_inst1/SLICE_337:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R3C17C.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/s_vnnp_pgood[1] (from clk_sys +)
Destination: FF Data in power_seq_inst1/s_vnnp_pgood[2] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay power_seq_inst1/SLICE_314 to power_seq_inst1/SLICE_314 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path power_seq_inst1/SLICE_314 to power_seq_inst1/SLICE_314:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C15B.CLK to R4C15B.Q0 power_seq_inst1/SLICE_314 (from clk_sys)
ROUTE 1 0.152 R4C15B.Q0 to R4C15B.M1 power_seq_inst1/s_vnnp_pgood[1] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to power_seq_inst1/SLICE_314:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R4C15B.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to power_seq_inst1/SLICE_314:
Name Fanout Delay (ns) Site Resource
ROUTE 248 1.216 OSC.OSC to R4C15B.CLK clk_sys
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_sys" 66.500000 MHz ; | 0.000 ns| 0.304 ns| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: LPC_CLK_c Source: LPC_CLK.PAD Loads: 27
No transfer within this clock domain is found
Clock Domain: clk_sys Source: OSCH_inst.OSC Loads: 248
Covered under: FREQUENCY NET "clk_sys" 66.500000 MHz ;
Data transfers from:
Clock Domain: LPC_CLK_c Source: LPC_CLK.PAD
Not reported because source and destination domains are unrelated.
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 43128 paths, 1 nets, and 2379 connections (80.92% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
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