Map TRACE Report
Loading design for application trce from file denverton_come_cpld_denverton_come_cpld_map.ncd.
Design name: COME_CPLD_TOP
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c1200.nph' in environment: E:/lattice 3.12/diamond/3.12/ispfpga.
Package Status: Final Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Mon May 24 11:28:41 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o Denverton_COMe_CPLD_Denverton_COMe_CPLD.tw1 -gui -msgset E:/work/COMe/C3000/COMe_V06/promote.xml Denverton_COMe_CPLD_Denverton_COMe_CPLD_map.ncd Denverton_COMe_CPLD_Denverton_COMe_CPLD.prf
Design file: denverton_come_cpld_denverton_come_cpld_map.ncd
Preference file: denverton_come_cpld_denverton_come_cpld.prf
Device,speed: LCMXO2-1200HC,4
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "clk_sys" 66.500000 MHz (4096 errors)
4096 items scored, 4096 timing errors detected.
Warning: 55.258MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "clk_sys" 66.500000 MHz ;
4096 items scored, 4096 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 3.059ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q power_seq_inst1/V1P05_CNT_868__i0 (from clk_sys +)
Destination: FF Data in power_seq_inst1/V1P05_CNT_868__i31 (to clk_sys +)
Delay: 17.931ns (46.4% logic, 53.6% route), 26 logic levels.
Constraint Details:
17.931ns physical path delay SLICE_77 to SLICE_61 exceeds
15.038ns delay constraint less
0.166ns DIN_SET requirement (totaling 14.872ns) by 3.059ns
Physical Path Details:
Data path SLICE_77 to SLICE_61:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 SLICE_77.CLK to SLICE_77.Q1 SLICE_77 (from clk_sys)
ROUTE 2 e 1.234 SLICE_77.Q1 to SLICE_459.A0 V1P05_CNT_0
CTOF_DEL --- 0.495 SLICE_459.A0 to SLICE_459.F0 SLICE_459
ROUTE 1 e 1.234 SLICE_459.F0 to */SLICE_370.A1 power_seq_inst1/n6_adj_1846
CTOF_DEL --- 0.495 */SLICE_370.A1 to */SLICE_370.F1 power_seq_inst1/SLICE_370
ROUTE 1 e 0.480 */SLICE_370.F1 to */SLICE_370.D0 power_seq_inst1/n12_adj_1844
CTOF_DEL --- 0.495 */SLICE_370.D0 to */SLICE_370.F0 power_seq_inst1/SLICE_370
ROUTE 1 e 1.234 */SLICE_370.F0 to */SLICE_367.A0 power_seq_inst1/n5_adj_1841
CTOF_DEL --- 0.495 */SLICE_367.A0 to */SLICE_367.F0 power_seq_inst1/SLICE_367
ROUTE 1 e 0.480 */SLICE_367.F0 to */SLICE_367.C1 power_seq_inst1/n24_adj_1842
CTOF_DEL --- 0.495 */SLICE_367.C1 to */SLICE_367.F1 power_seq_inst1/SLICE_367
ROUTE 1 e 1.234 */SLICE_367.F1 to SLICE_325.C1 power_seq_inst1/n10_adj_1982
CTOF_DEL --- 0.495 SLICE_325.C1 to SLICE_325.F1 SLICE_325
ROUTE 1 e 1.234 SLICE_325.F1 to */SLICE_411.B1 power_seq_inst1/n36_adj_1901
CTOF_DEL --- 0.495 */SLICE_411.B1 to */SLICE_411.F1 power_seq_inst1/SLICE_411
ROUTE 5 e 1.234 */SLICE_411.F1 to SLICE_459.C1 next_state_12_N_551_1
CTOF_DEL --- 0.495 SLICE_459.C1 to SLICE_459.F1 SLICE_459
ROUTE 1 e 1.234 SLICE_459.F1 to SLICE_77.C1 n6756
C1TOFCO_DE --- 0.889 SLICE_77.C1 to SLICE_77.FCO SLICE_77
ROUTE 1 e 0.001 SLICE_77.FCO to */SLICE_76.FCI power_seq_inst1/n7233
FCITOFCO_D --- 0.162 */SLICE_76.FCI to */SLICE_76.FCO power_seq_inst1/SLICE_76
ROUTE 1 e 0.001 */SLICE_76.FCO to */SLICE_75.FCI power_seq_inst1/n7234
FCITOFCO_D --- 0.162 */SLICE_75.FCI to */SLICE_75.FCO power_seq_inst1/SLICE_75
ROUTE 1 e 0.001 */SLICE_75.FCO to */SLICE_74.FCI power_seq_inst1/n7235
FCITOFCO_D --- 0.162 */SLICE_74.FCI to */SLICE_74.FCO power_seq_inst1/SLICE_74
ROUTE 1 e 0.001 */SLICE_74.FCO to */SLICE_73.FCI power_seq_inst1/n7236
FCITOFCO_D --- 0.162 */SLICE_73.FCI to */SLICE_73.FCO power_seq_inst1/SLICE_73
ROUTE 1 e 0.001 */SLICE_73.FCO to */SLICE_72.FCI power_seq_inst1/n7237
FCITOFCO_D --- 0.162 */SLICE_72.FCI to */SLICE_72.FCO power_seq_inst1/SLICE_72
ROUTE 1 e 0.001 */SLICE_72.FCO to */SLICE_71.FCI power_seq_inst1/n7238
FCITOFCO_D --- 0.162 */SLICE_71.FCI to */SLICE_71.FCO power_seq_inst1/SLICE_71
ROUTE 1 e 0.001 */SLICE_71.FCO to */SLICE_70.FCI power_seq_inst1/n7239
FCITOFCO_D --- 0.162 */SLICE_70.FCI to */SLICE_70.FCO power_seq_inst1/SLICE_70
ROUTE 1 e 0.001 */SLICE_70.FCO to */SLICE_69.FCI power_seq_inst1/n7240
FCITOFCO_D --- 0.162 */SLICE_69.FCI to */SLICE_69.FCO power_seq_inst1/SLICE_69
ROUTE 1 e 0.001 */SLICE_69.FCO to */SLICE_68.FCI power_seq_inst1/n7241
FCITOFCO_D --- 0.162 */SLICE_68.FCI to */SLICE_68.FCO power_seq_inst1/SLICE_68
ROUTE 1 e 0.001 */SLICE_68.FCO to */SLICE_67.FCI power_seq_inst1/n7242
FCITOFCO_D --- 0.162 */SLICE_67.FCI to */SLICE_67.FCO power_seq_inst1/SLICE_67
ROUTE 1 e 0.001 */SLICE_67.FCO to */SLICE_66.FCI power_seq_inst1/n7243
FCITOFCO_D --- 0.162 */SLICE_66.FCI to */SLICE_66.FCO power_seq_inst1/SLICE_66
ROUTE 1 e 0.001 */SLICE_66.FCO to */SLICE_65.FCI power_seq_inst1/n7244
FCITOFCO_D --- 0.162 */SLICE_65.FCI to */SLICE_65.FCO power_seq_inst1/SLICE_65
ROUTE 1 e 0.001 */SLICE_65.FCO to */SLICE_64.FCI power_seq_inst1/n7245
FCITOFCO_D --- 0.162 */SLICE_64.FCI to */SLICE_64.FCO power_seq_inst1/SLICE_64
ROUTE 1 e 0.001 */SLICE_64.FCO to */SLICE_63.FCI power_seq_inst1/n7246
FCITOFCO_D --- 0.162 */SLICE_63.FCI to */SLICE_63.FCO power_seq_inst1/SLICE_63
ROUTE 1 e 0.001 */SLICE_63.FCO to */SLICE_62.FCI power_seq_inst1/n7247
FCITOFCO_D --- 0.162 */SLICE_62.FCI to */SLICE_62.FCO power_seq_inst1/SLICE_62
ROUTE 1 e 0.001 */SLICE_62.FCO to SLICE_61.FCI power_seq_inst1/n7248
FCITOF0_DE --- 0.585 SLICE_61.FCI to SLICE_61.F0 SLICE_61
ROUTE 1 e 0.001 SLICE_61.F0 to SLICE_61.DI0 power_seq_inst1/n168_adj_1978 (to clk_sys)
--------
17.931 (46.4% logic, 53.6% route), 26 logic levels.
Warning: 55.258MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_sys" 66.500000 MHz ; | 66.500 MHz| 55.258 MHz| 26 *
| | |
----------------------------------------------------------------------------
1 preference(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
power_seq_inst1/n24_adj_1895 | 1| 1257| 30.69%
| | |
power_seq_inst1/n5_adj_1894 | 1| 1257| 30.69%
| | |
power_seq_inst1/n10_adj_1878 | 1| 1257| 30.69%
| | |
power_seq_inst1/n36_adj_1858 | 1| 1257| 30.69%
| | |
VDDQ_N_1145 | 4| 1257| 30.69%
| | |
power_seq_inst1/n12_adj_1822 | 1| 1257| 30.69%
| | |
power_seq_inst1/n6_adj_1821 | 1| 1194| 29.15%
| | |
power_seq_inst1/n989 | 31| 1140| 27.83%
| | |
power_seq_inst1/n7182 | 1| 822| 20.07%
| | |
power_seq_inst1/n7183 | 1| 822| 20.07%
| | |
power_seq_inst1/n7181 | 1| 798| 19.48%
| | |
power_seq_inst1/n7184 | 1| 798| 19.48%
| | |
power_seq_inst1/n7180 | 1| 750| 18.31%
| | |
power_seq_inst1/n7185 | 1| 750| 18.31%
| | |
power_seq_inst1/n7179 | 1| 678| 16.55%
| | |
power_seq_inst1/n7186 | 1| 678| 16.55%
| | |
power_seq_inst1/n7178 | 1| 582| 14.21%
| | |
power_seq_inst1/n7187 | 1| 582| 14.21%
| | |
power_seq_inst1/n10_adj_1982 | 1| 558| 13.62%
| | |
power_seq_inst1/n36_adj_1901 | 1| 558| 13.62%
| | |
next_state_12_N_551_1 | 5| 558| 13.62%
| | |
power_seq_inst1/n12_adj_1844 | 1| 558| 13.62%
| | |
power_seq_inst1/n24_adj_1842 | 1| 558| 13.62%
| | |
power_seq_inst1/n5_adj_1841 | 1| 558| 13.62%
| | |
power_seq_inst1/n12_adj_1896 | 1| 555| 13.55%
| | |
power_seq_inst1/n5_adj_1890 | 1| 555| 13.55%
| | |
power_seq_inst1/n24_adj_1889 | 1| 555| 13.55%
| | |
power_seq_inst1/n10_adj_1870 | 1| 555| 13.55%
| | |
power_seq_inst1/n36_adj_1862 | 1| 555| 13.55%
| | |
next_state_12_N_577_3 | 5| 555| 13.55%
| | |
power_seq_inst1/n6_adj_1846 | 1| 540| 13.18%
| | |
power_seq_inst1/n7272 | 1| 537| 13.11%
| | |
power_seq_inst1/n7273 | 1| 534| 13.04%
| | |
power_seq_inst1/n7271 | 1| 516| 12.60%
| | |
power_seq_inst1/n7240 | 1| 513| 12.52%
| | |
power_seq_inst1/n7274 | 1| 513| 12.52%
| | |
power_seq_inst1/n12_adj_1838 | 1| 512| 12.50%
| | |
power_seq_inst1/n5_adj_1837 | 1| 512| 12.50%
| | |
power_seq_inst1/n24_adj_1835 | 1| 512| 12.50%
| | |
power_seq_inst1/n10_adj_1828 | 1| 512| 12.50%
| | |
power_seq_inst1/n36_adj_1824 | 1| 512| 12.50%
| | |
next_state_12_N_499_1 | 7| 512| 12.50%
| | |
power_seq_inst1/n7241 | 1| 510| 12.45%
| | |
power_seq_inst1/n7151 | 1| 500| 12.21%
| | |
power_seq_inst1/n7150 | 1| 497| 12.13%
| | |
power_seq_inst1/n7239 | 1| 495| 12.08%
| | |
next_state_12_N_603_1 | 7| 494| 12.06%
| | |
power_seq_inst1/n6 | 1| 494| 12.06%
| | |
power_seq_inst1/n12 | 1| 494| 12.06%
| | |
power_seq_inst1/n5 | 1| 494| 12.06%
| | |
power_seq_inst1/n24_adj_1818 | 1| 494| 12.06%
| | |
power_seq_inst1/n36 | 1| 494| 12.06%
| | |
power_seq_inst1/n10 | 1| 494| 12.06%
| | |
power_seq_inst1/n6_adj_1897 | 1| 492| 12.01%
| | |
power_seq_inst1/n7242 | 1| 486| 11.87%
| | |
power_seq_inst1/n982 | 31| 485| 11.84%
| | |
power_seq_inst1/n7152 | 1| 483| 11.79%
| | |
power_seq_inst1/n857 | 31| 483| 11.79%
| | |
power_seq_inst1/n7270 | 1| 480| 11.72%
| | |
power_seq_inst1/n7275 | 1| 477| 11.65%
| | |
power_seq_inst1/n7134 | 1| 476| 11.62%
| | |
power_seq_inst1/n7135 | 1| 473| 11.55%
| | |
power_seq_inst1/n7149 | 1| 473| 11.55%
| | |
power_seq_inst1/n6_adj_1840 | 1| 467| 11.40%
| | |
power_seq_inst1/n7238 | 1| 465| 11.35%
| | |
power_seq_inst1/n7177 | 1| 459| 11.21%
| | |
power_seq_inst1/n7188 | 1| 456| 11.13%
| | |
power_seq_inst1/n7133 | 1| 455| 11.11%
| | |
power_seq_inst1/n7153 | 1| 453| 11.06%
| | |
power_seq_inst1/n7136 | 1| 450| 10.99%
| | |
power_seq_inst1/n7243 | 1| 450| 10.99%
| | |
power_seq_inst1/n851 | 31| 441| 10.77%
| | |
power_seq_inst1/n979 | 31| 440| 10.74%
| | |
power_seq_inst1/n7148 | 1| 437| 10.67%
| | |
power_seq_inst1/n7269 | 1| 432| 10.55%
| | |
power_seq_inst1/n7276 | 1| 429| 10.47%
| | |
power_seq_inst1/n7237 | 1| 423| 10.33%
| | |
power_seq_inst1/n7132 | 1| 419| 10.23%
| | |
power_seq_inst1/n7137 | 1| 414| 10.11%
| | |
power_seq_inst1/n7154 | 1| 411| 10.03%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: clk_sys Source: OSCH_inst.OSC Loads: 304
Covered under: FREQUENCY NET "clk_sys" 66.500000 MHz ;
Data transfers from:
Clock Domain: LPC_CLK_c Source: LPC_CLK.PAD
Not reported because source and destination domains are unrelated.
Clock Domain: LPC_CLK_c Source: LPC_CLK.PAD Loads: 35
No transfer within this clock domain is found
Timing summary (Setup):
---------------
Timing errors: 4096 Score: 5882768
Cumulative negative slack: 5882768
Constraints cover 181688 paths, 1 nets, and 3110 connections (84.58% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
Mon May 24 11:28:41 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o Denverton_COMe_CPLD_Denverton_COMe_CPLD.tw1 -gui -msgset E:/work/COMe/C3000/COMe_V06/promote.xml Denverton_COMe_CPLD_Denverton_COMe_CPLD_map.ncd Denverton_COMe_CPLD_Denverton_COMe_CPLD.prf
Design file: denverton_come_cpld_denverton_come_cpld_map.ncd
Preference file: denverton_come_cpld_denverton_come_cpld.prf
Device,speed: LCMXO2-1200HC,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "clk_sys" 66.500000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "clk_sys" 66.500000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.351ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q L_THERMTRIP_N_CON_i0_i1 (from clk_sys +)
Destination: FF Data in L_THERMTRIP_N_CON_i0_i2 (to clk_sys +)
Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
Constraint Details:
0.332ns physical path delay SLICE_195 to SLICE_195 meets
-0.019ns M_HLD and
0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
Physical Path Details:
Data path SLICE_195 to SLICE_195:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 SLICE_195.CLK to SLICE_195.Q0 SLICE_195 (from clk_sys)
ROUTE 2 e 0.199 SLICE_195.Q0 to SLICE_195.M1 L_THERMTRIP_N_CON_1 (to clk_sys)
--------
0.332 (40.1% logic, 59.9% route), 1 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_sys" 66.500000 MHz ; | 0.000 ns| 0.351 ns| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: clk_sys Source: OSCH_inst.OSC Loads: 304
Covered under: FREQUENCY NET "clk_sys" 66.500000 MHz ;
Data transfers from:
Clock Domain: LPC_CLK_c Source: LPC_CLK.PAD
Not reported because source and destination domains are unrelated.
Clock Domain: LPC_CLK_c Source: LPC_CLK.PAD Loads: 35
No transfer within this clock domain is found
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 181688 paths, 1 nets, and 3110 connections (84.58% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 4096 (setup), 0 (hold)
Score: 5882768 (setup), 0 (hold)
Cumulative negative slack: 5882768 (5882768+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------