I/O Timing Report Loading design for application iotiming from file denverton_come_cpld_denverton_come_cpld.ncd. Design name: COME_CPLD_TOP NCD version: 3.2 Vendor: LATTICE Device: LCMXO2-1200HC Package: TQFP100 Performance: 5 Package Status: Final Version 1.39 Performance Hardware Data Status: Final Version 23.4 Loading design for application iotiming from file denverton_come_cpld_denverton_come_cpld.ncd. Design name: COME_CPLD_TOP NCD version: 3.2 Vendor: LATTICE Device: LCMXO2-1200HC Package: TQFP100 Performance: 6 Package Status: Final Version 1.39 Performance Hardware Data Status: Final Version 23.4 Loading design for application iotiming from file denverton_come_cpld_denverton_come_cpld.ncd. Design name: COME_CPLD_TOP NCD version: 3.2 Vendor: LATTICE Device: LCMXO2-1200HC Package: TQFP100 Performance: M Package Status: Final Version 1.39 Performance Hardware Data Status: Final Version 23.4 // Design: COME_CPLD_TOP // Package: TQFP100 // ncd File: denverton_come_cpld_denverton_come_cpld.ncd // Version: Diamond Version 2.2.0.101 // Written on Wed Apr 26 10:05:52 2017 // M: Minimum Performance Grade // iotiming Denverton_COMe_CPLD_Denverton_COMe_CPLD.ncd Denverton_COMe_CPLD_Denverton_COMe_CPLD.prf I/O Timing Report (All units are in ns) Worst Case Results across Performance Grades (M, 6, 5, 4): // Input Setup and Hold Times Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- LPC_AD[0] LPC_CLK R -1.003 M 5.633 4 LPC_AD[1] LPC_CLK R -0.978 M 5.561 4 LPC_AD[2] LPC_CLK R -0.978 M 5.561 4 LPC_AD[3] LPC_CLK R -0.978 M 5.561 4 LPC_FRAME_N LPC_CLK R 4.309 4 2.224 4 PMU_PLTRST LPC_CLK R 4.013 4 -0.066 M // Clock to Output Delay Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ LPC_AD[0] LPC_CLK R 13.722 4 2.891 M LPC_AD[1] LPC_CLK R 14.861 4 2.891 M LPC_AD[2] LPC_CLK R 14.007 4 2.891 M LPC_AD[3] LPC_CLK R 13.146 4 2.891 M // Internal_Clock to Input Port Internal_Clock -------------------------------------------------------- CPLD_MEMHOT clk_sys_c GPIO38 clk_sys_c GPIO70 clk_sys_c IRQ_DIMM_EV clk_sys_c PMU_PLTRST clk_sys_c PMU_SLP_S3_ clk_sys_c PMU_SLP_S45 clk_sys_c PWR_OK clk_sys_c THERMTRIP_N clk_sys_c THRM_N clk_sys_c VCCP_PGOOD clk_sys_c VCCRAMP_PGO clk_sys_c VDDQP_PGOOD clk_sys_c VNNP_PGOOD clk_sys_c VRHOT clk_sys_c XP0R6V_PGOO clk_sys_c XP1R05V_PGO clk_sys_c XP1R24V_PGO clk_sys_c XP1R8V_PGOO clk_sys_c XP2R5V_PGOO clk_sys_c XP3R3V_PGOO clk_sys_c // Internal_Clock to Output Port Internal_Clock -------------------------------------------------------- CPLD_COREPWROK clk_sys_c CPLD_PROCHOT_N clk_sys_c EMMC_RST_N clk_sys_c RST_RSMRST_N clk_sys_c VCCP_EN clk_sys_c VCCRAMP_EN clk_sys_c VDDQP_EN clk_sys_c VNNP_EN clk_sys_c WDT_CON clk_sys_c XP0R6V_EN clk_sys_c XP1R05V_EN clk_sys_c XP1R24V_EN clk_sys_c XP1R8V_EN clk_sys_c XP2R5V_EN clk_sys_c