Lattice Synthesis Timing Report
--------------------------------------------------------------------------------
Lattice Synthesis Timing Report, Version
Mon May 24 11:28:37 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Design: COME_CPLD_TOP
Constraint file:
Report level: verbose report, limited to 3 items per constraint
--------------------------------------------------------------------------------
================================================================================
Constraint: create_clock -period 1000.000000 -name clk1 [get_nets LPC_CLK_c]
424 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 990.133ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3DX CK \LPC_inst1/data_read_count_FSM_i12 (from LPC_CLK_c +)
Destination: OFS1P3DX D \LPC_inst1/lad_o__i1 (to LPC_CLK_c +)
Delay: 9.646ns (30.2% logic, 69.8% route), 6 logic levels.
Constraint Details:
9.646ns data_path \LPC_inst1/data_read_count_FSM_i12 to \LPC_inst1/lad_o__i1 meets
1000.000ns delay constraint less
0.221ns I_S requirement (totaling 999.779ns) by 990.133ns
Path Details: \LPC_inst1/data_read_count_FSM_i12 to \LPC_inst1/lad_o__i1
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \LPC_inst1/data_read_count_FSM_i12 (from LPC_CLK_c)
Route 2 e 1.198 \LPC_inst1/n473
LUT4 --- 0.493 B to Z \LPC_inst1/i1_2_lut_adj_220
Route 1 e 0.941 \LPC_inst1/n6_adj_1810
LUT4 --- 0.493 D to Z \LPC_inst1/i4_4_lut_adj_219
Route 3 e 1.258 \LPC_inst1/n2945
LUT4 --- 0.493 C to Z \LPC_inst1/i1_2_lut_3_lut_adj_191
Route 3 e 1.258 \LPC_inst1/n3939
LUT4 --- 0.493 B to Z \LPC_inst1/i3444_4_lut
Route 2 e 1.141 \LPC_inst1/n3940
LUT4 --- 0.493 C to Z \LPC_inst1/i1_3_lut_4_lut_adj_221
Route 1 e 0.941 \LPC_inst1/n7
--------
9.646 (30.2% logic, 69.8% route), 6 logic levels.
Passed: The following path meets requirements by 990.133ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3DX CK \LPC_inst1/data_read_count_FSM_i12 (from LPC_CLK_c +)
Destination: OFS1P3DX D \LPC_inst1/lad_o__i2 (to LPC_CLK_c +)
Delay: 9.646ns (30.2% logic, 69.8% route), 6 logic levels.
Constraint Details:
9.646ns data_path \LPC_inst1/data_read_count_FSM_i12 to \LPC_inst1/lad_o__i2 meets
1000.000ns delay constraint less
0.221ns I_S requirement (totaling 999.779ns) by 990.133ns
Path Details: \LPC_inst1/data_read_count_FSM_i12 to \LPC_inst1/lad_o__i2
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \LPC_inst1/data_read_count_FSM_i12 (from LPC_CLK_c)
Route 2 e 1.198 \LPC_inst1/n473
LUT4 --- 0.493 B to Z \LPC_inst1/i1_2_lut_adj_220
Route 1 e 0.941 \LPC_inst1/n6_adj_1810
LUT4 --- 0.493 D to Z \LPC_inst1/i4_4_lut_adj_219
Route 3 e 1.258 \LPC_inst1/n2945
LUT4 --- 0.493 C to Z \LPC_inst1/i1_2_lut_3_lut_adj_191
Route 3 e 1.258 \LPC_inst1/n3939
LUT4 --- 0.493 B to Z \LPC_inst1/i3444_4_lut
Route 2 e 1.141 \LPC_inst1/n3940
LUT4 --- 0.493 C to Z \LPC_inst1/i1_3_lut_4_lut_adj_223
Route 1 e 0.941 \LPC_inst1/n6_adj_1811
--------
9.646 (30.2% logic, 69.8% route), 6 logic levels.
Passed: The following path meets requirements by 990.133ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3DX CK \LPC_inst1/data_read_count_FSM_i13 (from LPC_CLK_c +)
Destination: OFS1P3DX D \LPC_inst1/lad_o__i1 (to LPC_CLK_c +)
Delay: 9.646ns (30.2% logic, 69.8% route), 6 logic levels.
Constraint Details:
9.646ns data_path \LPC_inst1/data_read_count_FSM_i13 to \LPC_inst1/lad_o__i1 meets
1000.000ns delay constraint less
0.221ns I_S requirement (totaling 999.779ns) by 990.133ns
Path Details: \LPC_inst1/data_read_count_FSM_i13 to \LPC_inst1/lad_o__i1
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \LPC_inst1/data_read_count_FSM_i13 (from LPC_CLK_c)
Route 2 e 1.198 \LPC_inst1/n472
LUT4 --- 0.493 A to Z \LPC_inst1/i1_2_lut_adj_220
Route 1 e 0.941 \LPC_inst1/n6_adj_1810
LUT4 --- 0.493 D to Z \LPC_inst1/i4_4_lut_adj_219
Route 3 e 1.258 \LPC_inst1/n2945
LUT4 --- 0.493 C to Z \LPC_inst1/i1_2_lut_3_lut_adj_191
Route 3 e 1.258 \LPC_inst1/n3939
LUT4 --- 0.493 B to Z \LPC_inst1/i3444_4_lut
Route 2 e 1.141 \LPC_inst1/n3940
LUT4 --- 0.493 C to Z \LPC_inst1/i1_3_lut_4_lut_adj_221
Route 1 e 0.941 \LPC_inst1/n7
--------
9.646 (30.2% logic, 69.8% route), 6 logic levels.
Report: 9.867 ns is the maximum delay for this constraint.
================================================================================
Constraint: create_clock -period 1000.000000 -name clk0 [get_nets clk_sys]
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 980.205ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3DX CK \power_seq_inst1/VCC_EN_CNT_858__i0 (from clk_sys +)
Destination: FD1S3DX D \power_seq_inst1/VCC_EN_CNT_858__i31 (to clk_sys +)
Delay: 19.635ns (40.8% logic, 59.2% route), 25 logic levels.
Constraint Details:
19.635ns data_path \power_seq_inst1/VCC_EN_CNT_858__i0 to \power_seq_inst1/VCC_EN_CNT_858__i31 meets
1000.000ns delay constraint less
0.160ns L_S requirement (totaling 999.840ns) by 980.205ns
Path Details: \power_seq_inst1/VCC_EN_CNT_858__i0 to \power_seq_inst1/VCC_EN_CNT_858__i31
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \power_seq_inst1/VCC_EN_CNT_858__i0 (from clk_sys)
Route 2 e 1.198 VCC_EN_CNT[0]
LUT4 --- 0.493 A to Z \power_seq_inst1/i1573_3_lut
Route 1 e 0.941 \power_seq_inst1/n6
LUT4 --- 0.493 A to Z \power_seq_inst1/i1172_4_lut
Route 1 e 0.941 \power_seq_inst1/n12
LUT4 --- 0.493 D to Z \power_seq_inst1/i1_4_lut
Route 1 e 0.941 \power_seq_inst1/n5
LUT4 --- 0.493 A to Z \power_seq_inst1/i1577_4_lut
Route 1 e 0.941 \power_seq_inst1/n24_adj_1818
LUT4 --- 0.493 C to Z \power_seq_inst1/i4_4_lut
Route 1 e 0.941 \power_seq_inst1/n10
LUT4 --- 0.493 C to Z \power_seq_inst1/i1578_4_lut
Route 1 e 0.941 \power_seq_inst1/n36
LUT4 --- 0.493 B to Z \power_seq_inst1/i7177_4_lut
Route 7 e 1.502 next_state_12__N_603[1]
LUT4 --- 0.493 C to Z \power_seq_inst1/i636_2_lut_3_lut
Route 31 e 2.037 \power_seq_inst1/n979
A1_TO_FCO --- 0.827 B[2] to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_3
Route 1 e 0.020 \power_seq_inst1/n7128
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_5
Route 1 e 0.020 \power_seq_inst1/n7129
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_7
Route 1 e 0.020 \power_seq_inst1/n7130
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_9
Route 1 e 0.020 \power_seq_inst1/n7131
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_11
Route 1 e 0.020 \power_seq_inst1/n7132
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_13
Route 1 e 0.020 \power_seq_inst1/n7133
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_15
Route 1 e 0.020 \power_seq_inst1/n7134
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_17
Route 1 e 0.020 \power_seq_inst1/n7135
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_19
Route 1 e 0.020 \power_seq_inst1/n7136
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_21
Route 1 e 0.020 \power_seq_inst1/n7137
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_23
Route 1 e 0.020 \power_seq_inst1/n7138
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_25
Route 1 e 0.020 \power_seq_inst1/n7139
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_27
Route 1 e 0.020 \power_seq_inst1/n7140
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_29
Route 1 e 0.020 \power_seq_inst1/n7141
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_31
Route 1 e 0.020 \power_seq_inst1/n7142
FCI_TO_F --- 0.598 CIN to S[2] \power_seq_inst1/VCC_EN_CNT_858_add_4_33
Route 1 e 0.941 \power_seq_inst1/n168_adj_2179
--------
19.635 (40.8% logic, 59.2% route), 25 logic levels.
Passed: The following path meets requirements by 980.205ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3DX CK \power_seq_inst1/VCC_EN_CNT_858__i0 (from clk_sys +)
Destination: FD1S3DX D \power_seq_inst1/VCC_EN_CNT_858__i31 (to clk_sys +)
Delay: 19.635ns (40.8% logic, 59.2% route), 25 logic levels.
Constraint Details:
19.635ns data_path \power_seq_inst1/VCC_EN_CNT_858__i0 to \power_seq_inst1/VCC_EN_CNT_858__i31 meets
1000.000ns delay constraint less
0.160ns L_S requirement (totaling 999.840ns) by 980.205ns
Path Details: \power_seq_inst1/VCC_EN_CNT_858__i0 to \power_seq_inst1/VCC_EN_CNT_858__i31
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \power_seq_inst1/VCC_EN_CNT_858__i0 (from clk_sys)
Route 2 e 1.198 VCC_EN_CNT[0]
LUT4 --- 0.493 A to Z \power_seq_inst1/i1573_3_lut
Route 1 e 0.941 \power_seq_inst1/n6
LUT4 --- 0.493 A to Z \power_seq_inst1/i1172_4_lut
Route 1 e 0.941 \power_seq_inst1/n12
LUT4 --- 0.493 D to Z \power_seq_inst1/i1_4_lut
Route 1 e 0.941 \power_seq_inst1/n5
LUT4 --- 0.493 A to Z \power_seq_inst1/i1577_4_lut
Route 1 e 0.941 \power_seq_inst1/n24_adj_1818
LUT4 --- 0.493 C to Z \power_seq_inst1/i4_4_lut
Route 1 e 0.941 \power_seq_inst1/n10
LUT4 --- 0.493 C to Z \power_seq_inst1/i1578_4_lut
Route 1 e 0.941 \power_seq_inst1/n36
LUT4 --- 0.493 B to Z \power_seq_inst1/i7177_4_lut
Route 7 e 1.502 next_state_12__N_603[1]
LUT4 --- 0.493 C to Z \power_seq_inst1/i636_2_lut_3_lut
Route 31 e 2.037 \power_seq_inst1/n979
A1_TO_FCO --- 0.827 B[2] to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_3
Route 1 e 0.020 \power_seq_inst1/n7128
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_5
Route 1 e 0.020 \power_seq_inst1/n7129
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_7
Route 1 e 0.020 \power_seq_inst1/n7130
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_9
Route 1 e 0.020 \power_seq_inst1/n7131
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_11
Route 1 e 0.020 \power_seq_inst1/n7132
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_13
Route 1 e 0.020 \power_seq_inst1/n7133
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_15
Route 1 e 0.020 \power_seq_inst1/n7134
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_17
Route 1 e 0.020 \power_seq_inst1/n7135
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_19
Route 1 e 0.020 \power_seq_inst1/n7136
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_21
Route 1 e 0.020 \power_seq_inst1/n7137
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_23
Route 1 e 0.020 \power_seq_inst1/n7138
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_25
Route 1 e 0.020 \power_seq_inst1/n7139
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_27
Route 1 e 0.020 \power_seq_inst1/n7140
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_29
Route 1 e 0.020 \power_seq_inst1/n7141
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCC_EN_CNT_858_add_4_31
Route 1 e 0.020 \power_seq_inst1/n7142
FCI_TO_F --- 0.598 CIN to S[2] \power_seq_inst1/VCC_EN_CNT_858_add_4_33
Route 1 e 0.941 \power_seq_inst1/n168_adj_2179
--------
19.635 (40.8% logic, 59.2% route), 25 logic levels.
Passed: The following path meets requirements by 980.205ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3DX CK \power_seq_inst1/VCCRAM_CNT_860__i0 (from clk_sys +)
Destination: FD1S3DX D \power_seq_inst1/VCCRAM_CNT_860__i31 (to clk_sys +)
Delay: 19.635ns (40.8% logic, 59.2% route), 25 logic levels.
Constraint Details:
19.635ns data_path \power_seq_inst1/VCCRAM_CNT_860__i0 to \power_seq_inst1/VCCRAM_CNT_860__i31 meets
1000.000ns delay constraint less
0.160ns L_S requirement (totaling 999.840ns) by 980.205ns
Path Details: \power_seq_inst1/VCCRAM_CNT_860__i0 to \power_seq_inst1/VCCRAM_CNT_860__i31
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \power_seq_inst1/VCCRAM_CNT_860__i0 (from clk_sys)
Route 2 e 1.198 VCCRAM_CNT[0]
LUT4 --- 0.493 A to Z \power_seq_inst1/i1580_3_lut
Route 1 e 0.941 \power_seq_inst1/n6_adj_1840
LUT4 --- 0.493 A to Z \power_seq_inst1/i1203_4_lut
Route 1 e 0.941 \power_seq_inst1/n12_adj_1838
LUT4 --- 0.493 D to Z \power_seq_inst1/i1_4_lut_adj_251
Route 1 e 0.941 \power_seq_inst1/n5_adj_1837
LUT4 --- 0.493 A to Z \power_seq_inst1/i1584_4_lut
Route 1 e 0.941 \power_seq_inst1/n24_adj_1835
LUT4 --- 0.493 C to Z \power_seq_inst1/i4_4_lut_adj_250
Route 1 e 0.941 \power_seq_inst1/n10_adj_1828
LUT4 --- 0.493 C to Z \power_seq_inst1/i1585_4_lut
Route 1 e 0.941 \power_seq_inst1/n36_adj_1824
LUT4 --- 0.493 B to Z \power_seq_inst1/i7166_4_lut
Route 7 e 1.502 next_state_12__N_499[1]
LUT4 --- 0.493 C to Z \power_seq_inst1/i639_2_lut_3_lut
Route 31 e 2.037 \power_seq_inst1/n982
A1_TO_FCO --- 0.827 B[2] to COUT \power_seq_inst1/VCCRAM_CNT_860_add_4_3
Route 1 e 0.020 \power_seq_inst1/n7144
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCCRAM_CNT_860_add_4_5
Route 1 e 0.020 \power_seq_inst1/n7145
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCCRAM_CNT_860_add_4_7
Route 1 e 0.020 \power_seq_inst1/n7146
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCCRAM_CNT_860_add_4_9
Route 1 e 0.020 \power_seq_inst1/n7147
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCCRAM_CNT_860_add_4_11
Route 1 e 0.020 \power_seq_inst1/n7148
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCCRAM_CNT_860_add_4_13
Route 1 e 0.020 \power_seq_inst1/n7149
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCCRAM_CNT_860_add_4_15
Route 1 e 0.020 \power_seq_inst1/n7150
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCCRAM_CNT_860_add_4_17
Route 1 e 0.020 \power_seq_inst1/n7151
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCCRAM_CNT_860_add_4_19
Route 1 e 0.020 \power_seq_inst1/n7152
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCCRAM_CNT_860_add_4_21
Route 1 e 0.020 \power_seq_inst1/n7153
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCCRAM_CNT_860_add_4_23
Route 1 e 0.020 \power_seq_inst1/n7154
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCCRAM_CNT_860_add_4_25
Route 1 e 0.020 \power_seq_inst1/n7155
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCCRAM_CNT_860_add_4_27
Route 1 e 0.020 \power_seq_inst1/n7156
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCCRAM_CNT_860_add_4_29
Route 1 e 0.020 \power_seq_inst1/n7157
FCI_TO_FCO --- 0.157 CIN to COUT \power_seq_inst1/VCCRAM_CNT_860_add_4_31
Route 1 e 0.020 \power_seq_inst1/n7158
FCI_TO_F --- 0.598 CIN to S[2] \power_seq_inst1/VCCRAM_CNT_860_add_4_33
Route 1 e 0.941 \power_seq_inst1/n168_adj_2148
--------
19.635 (40.8% logic, 59.2% route), 25 logic levels.
Report: 19.795 ns is the maximum delay for this constraint.
Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint | Constraint| Actual|Levels
--------------------------------------------------------------------------------
| | |
create_clock -period 1000.000000 -name | | |
clk1 [get_nets LPC_CLK_c] | 1000.000 ns| 9.867 ns| 6
| | |
create_clock -period 1000.000000 -name | | |
clk0 [get_nets clk_sys] | 1000.000 ns| 19.795 ns| 25
| | |
--------------------------------------------------------------------------------
All constraints were met.
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 187412 paths, 1595 nets, and 4195 connections (92.1% coverage)
Peak memory: 82722816 bytes, TRCE: 15241216 bytes, DLYMAN: 491520 bytes
CPU_TIME_REPORT: 0 secs