@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":910:1:910:6|Removing instance come_bios_dis_reg[3] because it is equivalent to instance come_bios_dis_reg[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1357:1:1357:6|Removing instance reset_source_reg[4] because it is equivalent to instance reset_source_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1357:1:1357:6|Removing instance reset_source_reg[7] because it is equivalent to instance reset_source_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1357:1:1357:6|Removing instance reset_source_reg[5] because it is equivalent to instance reset_source_reg[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1357:1:1357:6|Removing instance reset_source_reg[6] because it is equivalent to instance reset_source_reg[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\com_exp_ctrl.v":83:1:83:6|Removing instance com_exp_ctrl_inst1.s_com_sus_sta[0] because it is equivalent to instance cb_rst_n[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MT420 |Found inferred clock Belgite_BOARD_CPLD|clk_sys_inferred_clock with period 15.04ns. Please declare a user-defined clock on net clk_sys.
@W: MT420 |Found inferred clock Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK with period 10.00ns. Please declare a user-defined clock on port COME_CPLD_LPC_CLK.
