@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1731:25:1731:28|Tristate driver o_r_sata_pcie_sel (in view: work.Belgite_BOARD_CPLD(verilog)) on net o_r_sata_pcie_sel (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":166:24:166:36|Tristate driver R_TPM_LPCPD_L (in view: work.Belgite_BOARD_CPLD(verilog)) on net R_TPM_LPCPD_L (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1731:25:1731:28|Tristate driver COME_WAKE_N (in view: work.Belgite_BOARD_CPLD(verilog)) on net COME_WAKE_N (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1731:25:1731:28|Tristate driver CB_THRM_N (in view: work.Belgite_BOARD_CPLD(verilog)) on net CB_THRM_N (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1731:25:1731:28|Tristate driver PEWAKE1_N (in view: work.Belgite_BOARD_CPLD(verilog)) on net PEWAKE1_N (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1731:25:1731:28|Tristate driver UCD_LATE_CNTRL_C (in view: work.Belgite_BOARD_CPLD(verilog)) on net UCD_LATE_CNTRL_C (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
@N: MO111 :|Tristate driver led2_t (in view: work.Belgite_BOARD_CPLD(verilog)) on net led2 (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":2255:1:2255:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance cnt_300s[8:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1175:1:1175:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance watch_dog_rst_cnt[8:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1321:1:1321:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance cb_rst_dly[5:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1302:1:1302:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance cb_rstp_dly[3:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1083:1:1083:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance cb_rst_l_cnt[5:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":2650:1:2650:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance led_cnt[7:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":681:4:681:9|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance PWR_GD_EARLY_CNT[7:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":699:4:699:9|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance B50282_RST_CNT[6:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":338:1:338:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance internal_por_cnt[4:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":2094:1:2094:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance clk_200ms_count_fan3[7:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":2010:1:2010:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance clk_200ms_count_fan2[7:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1928:1:1928:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance clk_200ms_count_fan1[7:0] 
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":910:1:910:6|Removing sequential instance come_bios_dis_reg[2] (in view: work.Belgite_BOARD_CPLD(verilog)) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\lpc_io_cycle.v":201:4:201:9|Removing sequential instance data_addr[15] (in view: work.LPC_IO_CYCLE_Z1(verilog)) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\lpc_io_cycle.v":201:4:201:9|Removing sequential instance data_addr[14] (in view: work.LPC_IO_CYCLE_Z1(verilog)) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\lpc_io_cycle.v":201:4:201:9|Removing sequential instance data_addr[13] (in view: work.LPC_IO_CYCLE_Z1(verilog)) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\lpc_io_cycle.v":201:4:201:9|Removing sequential instance data_addr[12] (in view: work.LPC_IO_CYCLE_Z1(verilog)) because it does not drive other instances.
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\lpc_io_cycle.v":100:4:100:9|Found counter in view:work.LPC_IO_CYCLE_Z1(verilog) instance data_write_count[3:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\lpc_io_cycle.v":83:4:83:9|Found counter in view:work.LPC_IO_CYCLE_Z1(verilog) instance data_read_count[3:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\power_on_seq.v":438:1:438:6|Found counter in view:work.power_on_seq(verilog) instance open_sw_power_cnt[7:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\power_on_seq.v":345:1:345:6|Found counter in view:work.power_on_seq(verilog) instance powr_off_sta_cnt[3:0] 
@N: FX493 |Applying initial value "0" on instance delay_cnt_1v8_1v2_0v8[0].
@N: FX493 |Applying initial value "0" on instance delay_cnt_1v8_1v2_0v8[1].
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\com_exp_ctrl.v":553:4:553:9|Found counter in view:work.com_exp_ctrl(verilog) instance boot_cnt[9:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\com_exp_ctrl.v":341:1:341:6|Found counter in view:work.com_exp_ctrl(verilog) instance pwrbtn_tri_dly[4:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\com_exp_ctrl.v":530:4:530:9|Found counter in view:work.com_exp_ctrl(verilog) instance pwr_force_count[3:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\com_exp_ctrl.v":507:4:507:9|Found counter in view:work.com_exp_ctrl(verilog) instance pwr_on_std_count[3:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\com_exp_ctrl.v":361:4:361:9|Found counter in view:work.com_exp_ctrl(verilog) instance wait_s0_cnt[3:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\com_exp_ctrl.v":289:4:289:9|Found counter in view:work.com_exp_ctrl(verilog) instance back_up_cnt[4:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\wd_ctrl.v":127:1:127:6|Found counter in view:work.Wd_Ctrl(verilog) instance s_loss_count[7:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\fan_ctrl.v":85:0:85:5|Found counter in view:work.fan_ctrl_2(verilog) instance fan1_sense_counter[7:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\fan_ctrl.v":51:0:51:5|Found counter in view:work.fan_ctrl_2(verilog) instance counterPWM1[7:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\fan_ctrl.v":85:0:85:5|Found counter in view:work.fan_ctrl_1(verilog) instance fan1_sense_counter[7:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\fan_ctrl.v":51:0:51:5|Found counter in view:work.fan_ctrl_1(verilog) instance counterPWM1[7:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\fan_ctrl.v":85:0:85:5|Found counter in view:work.fan_ctrl_0(verilog) instance fan1_sense_counter[7:0] 
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\fan_ctrl.v":51:0:51:5|Found counter in view:work.fan_ctrl_0(verilog) instance counterPWM1[7:0] 
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\com_exp_ctrl.v":591:4:591:9|Removing sequential instance com_exp_ctrl_inst1.o_bios_dis_n[0] (in view: work.Belgite_BOARD_CPLD(verilog)) because it does not drive other instances.
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":19:21:19:24|Tristate driver led2_obuft.un1[0] (in view: work.Belgite_BOARD_CPLD(verilog)) on net led2 (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":21:21:21:36|Tristate driver UCD_LATE_CNTRL_C_obuft.un1[0] (in view: work.Belgite_BOARD_CPLD(verilog)) on net UCD_LATE_CNTRL_C (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":57:22:57:30|Tristate driver PEWAKE1_N_obuft.un1[0] (in view: work.Belgite_BOARD_CPLD(verilog)) on net PEWAKE1_N (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
@N: FX1056 |Writing EDF file: E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\impl1\M0_CPLD_V25_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
