@W: CG921 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":755:13:755:16|led2 is already declared in this scope.
@W: CG1249 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":974:22:974:37|Redeclaration of implicit signal com_exp_ctrl_sta
@W: CG1249 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1662:20:1662:32|Redeclaration of implicit signal thm_shutdwn_n
@W: CG921 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1873:15:1873:30|sysled_green_tem is already declared in this scope.
@W: CG921 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1874:15:1874:30|sysled_amber_tem is already declared in this scope.
@W: CG921 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1908:28:1908:44|come_pwr_ctrl_reg is already declared in this scope.
@W: CG1249 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2229:14:2229:25|Redeclaration of implicit signal fan1_pwm_out
@W: CG1249 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2230:14:2230:25|Redeclaration of implicit signal fan2_pwm_out
@W: CG1249 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2231:14:2231:25|Redeclaration of implicit signal fan3_pwm_out
@W: CG1337 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2540:9:2540:22|Net PRT_LPMD_TXDIS is not declared.
@W: CG1337 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2710:9:2710:24|Net IPROC_LED1_CLK_C is not declared.
@W: CG1337 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2711:9:2711:25|Net IPROC_LED1_DATA_C is not declared.
@W: CG1337 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2725:8:2725:24|Net o_tpm_lpc_reset_n is not declared.
@W: CG921 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":341:6:341:19|power_off_flag is already declared in this scope.
@W: CG921 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":373:5:373:18|pwr_en_0v8_avs is already declared in this scope.
@W: CG360 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":53:24:53:37|Removing wire SYS_CB_1R0V_PG, as there is no assignment to it.
@W: CG360 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":54:24:54:37|Removing wire SYS_CB_3R3V_PG, as there is no assignment to it.
@W: CG360 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":57:24:57:27|Removing wire led2, as there is no assignment to it.
@W: CG360 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":58:24:58:39|Removing wire curr_state_debug, as there is no assignment to it.
@W: CG360 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":97:6:97:19|Removing wire delay_done_3v3, as there is no assignment to it.
@W: CG360 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":98:6:98:19|Removing wire delay_done_1v0, as there is no assignment to it.
@W: CG360 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":99:6:99:23|Removing wire delay_done_0v8_avs, as there is no assignment to it.
@W: CL318 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":53:24:53:37|*Output SYS_CB_1R0V_PG has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":54:24:54:37|*Output SYS_CB_3R3V_PG has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":57:24:57:27|*Output led2 has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":58:24:58:39|*Output curr_state_debug has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CG360 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":67:15:67:28|Removing wire en_12v_cpu_dly, as there is no assignment to it.
@W: CL168 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":665:14:665:29|Removing instance inst_pwrgd_stby5 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL169 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":308:4:308:9|Pruning unused register cpu_s5_count[2:0]. Make sure that there are no unused intermediate registers.
@W: CG532 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":337:1:337:7|Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored. Simulation mismatch may occur
@W: CG1340 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2676:28:2676:39|Index into variable led_data could be out of range ; a simulation mismatch is possible.
@W: CG781 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1989:10:1989:18|Input i_fan_led_ctrl on instance fan1_ctrl is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2072:10:2072:18|Input i_fan_led_ctrl on instance fan2_ctrl is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2156:10:2156:18|Input i_fan_led_ctrl on instance fan3_ctrl is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG360 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":166:24:166:36|Removing wire R_TPM_LPCPD_L, as there is no assignment to it.
@W: CL318 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":166:24:166:36|*Output R_TPM_LPCPD_L has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL169 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1342:1:1342:6|Pruning unused register cp_cold_rst_flag. Make sure that there are no unused intermediate registers.
@W: CL271 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2504:1:2504:6|Pruning unused bits 7 to 5 of psu_force_ctrl[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2504:1:2504:6|Pruning unused bits 3 to 2 of psu_force_ctrl[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL265 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2118:1:2118:6|Removing unused bit 2 of fan3_tach_dly[2:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2034:1:2034:6|Removing unused bit 2 of fan2_tach_dly[2:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1952:1:1952:6|Removing unused bit 2 of fan1_tach_dly[2:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1238:1:1238:6|Removing unused bit 2 of power_cycle_dly[2:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1230:1:1230:6|Removing unused bit 2 of cb_sus_s3[2:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1222:1:1222:6|Removing unused bit 2 of pwr_btn_r[2:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1167:1:1167:6|Removing unused bit 2 of watch_dog_rst_r[2:0]. Either assign all bits or reduce the width of the signal.
@W: CL113 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|Feedback mux created for signal led_data[15:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL251 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[15] assign 1, register removed by optimization
@W: CL250 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[14] assign 0, register removed by optimization
@W: CL251 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[13] assign 1, register removed by optimization
@W: CL250 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[12] assign 0, register removed by optimization
@W: CL251 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[11] assign 1, register removed by optimization
@W: CL250 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[10] assign 0, register removed by optimization
@W: CL251 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[9] assign 1, register removed by optimization
@W: CL250 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[8] assign 0, register removed by optimization
@W: CL251 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[7] assign 1, register removed by optimization
@W: CL250 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[6] assign 0, register removed by optimization
@W: CL251 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[5] assign 1, register removed by optimization
@W: CL250 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[4] assign 0, register removed by optimization
@W: CL251 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[3] assign 1, register removed by optimization
@W: CL250 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[2] assign 0, register removed by optimization
@W: CL251 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[1] assign 1, register removed by optimization
@W: CL250 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[0] assign 0, register removed by optimization
@W: CL190 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1959:1:1959:6|Optimizing register bit FAN1_PRESENT_CNT[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2042:1:2042:6|Optimizing register bit FAN2_PRESENT_CNT[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2126:1:2126:6|Optimizing register bit FAN3_PRESENT_CNT[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":605:1:605:6|Optimizing register bit sw_rst_cnt[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":605:1:605:6|Optimizing register bit sw_rst_cnt[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":605:1:605:6|Pruning register bits 10 to 9 of sw_rst_cnt[10:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2126:1:2126:6|Pruning register bit 2 of FAN3_PRESENT_CNT[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2042:1:2042:6|Pruning register bit 2 of FAN2_PRESENT_CNT[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1959:1:1959:6|Pruning register bit 2 of FAN1_PRESENT_CNT[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":338:1:338:6|Pruning register bit 5 of internal_por_cnt[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL246 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\watchdog.v":20:24:20:36|Input port bits 15 to 8 of lpc_data_addr[15:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL190 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":553:4:553:9|Optimizing register bit boot_cnt[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":553:4:553:9|Optimizing register bit boot_cnt[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":553:4:553:9|Pruning register bits 11 to 10 of boot_cnt[11:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL190 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":287:1:287:6|Optimizing register bit delay_cnt_1v8_1v2_0v8[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":287:1:287:6|Optimizing register bit delay_cnt_1v8_1v2_0v8[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":287:1:287:6|Pruning register bits 3 to 2 of delay_cnt_1v8_1v2_0v8[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL249 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":89:1:89:6|Initial value is not supported on state machine C_State

