#--  Synopsys, Inc.
#--  Version Q-2020.03L-SP1
#--  Project file E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\impl1\run_options.txt
#--  Written on Mon Dec  6 18:57:02 2021


#project files
add_file -verilog -vlog_std v2001 "E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v"
add_file -verilog -vlog_std v2001 "E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/cfg_int_gen.v"
add_file -verilog -vlog_std v2001 "E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/com_exp_ctrl.v"
add_file -verilog -vlog_std v2001 "E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/delay_mod.v"
add_file -verilog -vlog_std v2001 "E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/fan_ctrl.v"
add_file -verilog -vlog_std v2001 "E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/i2c_slave.v"
add_file -verilog -vlog_std v2001 "E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/LPC_IO_CYCLE.v"
add_file -verilog -vlog_std v2001 "E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/power_on_seq.v"
add_file -verilog -vlog_std v2001 "E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/watchdog.v"
add_file -verilog -vlog_std v2001 "E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Wd_Ctrl.v"


#implementation: "impl1"
impl -add impl1 -type fpga

#
#implementation attributes

set_option -vlog_std v2001
set_option -project_relative_includes 1
set_option -include_path {E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb}

#device options
set_option -technology MACHXO2
set_option -part LCMXO2_2000HC
set_option -package FTG256C
set_option -speed_grade -4
set_option -part_companion ""

#compilation/mapping options
set_option -top_module "Belgite_BOARD_CPLD"

# hdl_compiler_options
set_option -distributed_compile 0
set_option -hdl_strict_syntax 0

# mapper_without_write_options
set_option -frequency 100
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# Lattice XP
set_option -maxfan 1000
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 1
set_option -forcegsr false
set_option -fix_gated_and_generated_clocks 1
set_option -rw_check_on_ram 1
set_option -update_models_cp 0
set_option -syn_edif_array_rename 1
set_option -Write_declared_clocks_only 1
set_option -seqshift_no_replicate 0

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./M0_CPLD_V25_impl1.edi"

#set log file 
set_option log_file "E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/impl1/M0_CPLD_V25_impl1.srf" 
impl -active "impl1"
