Setting log file to 'E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/impl1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file 'E:/lattice 3.12/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
(VERI-1482) Analyzing Verilog file 'E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v'
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(755,14-755,18) (VERI-1372) redeclaration of ansi port 'led2' is not allowed
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(974,23-974,39) (VERI-1362) 'com_exp_ctrl_sta' is already implicitly declared on line 969
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1662,21-1662,34) (VERI-1362) 'thm_shutdwn_n' is already implicitly declared on line 770
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1873,16-1873,32) (VERI-1372) redeclaration of ansi port 'sysled_green_tem' is not allowed
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1874,16-1874,32) (VERI-1372) redeclaration of ansi port 'sysled_amber_tem' is not allowed
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1908,29-1908,46) (VERI-2170) data object 'come_pwr_ctrl_reg' is already declared
INFO - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(311,21-311,38) (VERI-1967) previous declaration of 'come_pwr_ctrl_reg' is from here
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1908,29-1908,46) (VERI-1329) second declaration of 'come_pwr_ctrl_reg' ignored
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(2229,15-2229,27) (VERI-1362) 'fan1_pwm_out' is already implicitly declared on line 1995
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(2230,15-2230,27) (VERI-1362) 'fan2_pwm_out' is already implicitly declared on line 2078
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(2231,15-2231,27) (VERI-1362) 'fan3_pwm_out' is already implicitly declared on line 2162
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(2542,24-2542,38) (VERI-1362) 'PRT_LPMD_TXDIS' is already implicitly declared on line 2540
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(2559,9-2559,24) (VERI-1362) 'sw_power_on_reg' is already implicitly declared on line 769
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(627,28-627,49) (VERI-1875) identifier 'bcm56277_rst_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(628,31-628,52) (VERI-1875) identifier 'bcm56277_rst_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(629,32-629,44) (VERI-1875) identifier 'FAN_LED_sign' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(629,49-629,65) (VERI-1875) identifier 'PWR_GD_EARLY_CNT' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(630,32-630,44) (VERI-1875) identifier 'FAN_LED_sign' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(631,36-631,48) (VERI-1875) identifier 'rst_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(632,32-632,44) (VERI-1875) identifier 'FAN_LED_sign' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(632,55-632,76) (VERI-1875) identifier 'bcm56277_rst_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(633,33-633,45) (VERI-1875) identifier 'rst_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(634,33-634,45) (VERI-1875) identifier 'rst_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(635,33-635,45) (VERI-1875) identifier 'rst_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(636,33-636,45) (VERI-1875) identifier 'rst_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(637,33-637,47) (VERI-1875) identifier 'B50282_RST_CNT' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(637,63-637,77) (VERI-1875) identifier 'phy1_reset_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(638,33-638,47) (VERI-1875) identifier 'B50282_RST_CNT' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(638,63-638,77) (VERI-1875) identifier 'phy2_reset_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(639,33-639,47) (VERI-1875) identifier 'B50282_RST_CNT' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(639,63-639,77) (VERI-1875) identifier 'phy3_reset_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(942,93-942,106) (VERI-1875) identifier 'pw_cycle_sign' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(944,45-944,59) (VERI-1875) identifier 'watch_dog_rstn' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1328,12-1328,24) (VERI-1875) identifier 'FAN_LED_sign' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1373,18-1373,34) (VERI-1875) identifier 'overload_sta_r_t' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1375,15-1375,31) (VERI-1875) identifier 'overload_sta_r_t' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1377,15-1377,31) (VERI-1875) identifier 'overload_sta_r_t' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1447,55-1447,65) (VERI-1875) identifier 's_cpu_sus0' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1448,54-1448,63) (VERI-1875) identifier 's_int_sta' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1449,54-1449,63) (VERI-1875) identifier 's_int0_do' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1450,54-1450,67) (VERI-1875) identifier 'int0_mask_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1451,55-1451,65) (VERI-1875) identifier 's_cpu_sus1' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1452,54-1452,64) (VERI-1875) identifier 's_int1_sta' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1453,54-1453,63) (VERI-1875) identifier 's_int1_do' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1454,54-1454,67) (VERI-1875) identifier 'int1_mask_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1466,53-1466,67) (VERI-1875) identifier 'over_time_flag' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1466,74-1466,88) (VERI-1875) identifier 'fan_wdt_en_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1477,54-1477,69) (VERI-1875) identifier 'SI5332_CTRL_OUT' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1478,50-1478,66) (VERI-1875) identifier 'PRT_PRSNT_MODABS' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1479,50-1479,63) (VERI-1875) identifier 'PRT_INT_RXLOS' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1480,49-1480,63) (VERI-1875) identifier 'PRT_MDSL_TXFLT' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1481,49-1481,68) (VERI-1875) identifier 'prt_lpmod_txdis_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1484,53-1484,71) (VERI-1875) identifier 'front_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1485,53-1485,71) (VERI-1875) identifier 'alarm_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1489,53-1489,64) (VERI-1875) identifier 'thm_ctrl_en' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1499,40-1499,54) (VERI-1875) identifier 'overload_sta_r' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1509,53-1509,66) (VERI-1875) identifier 'fan_misc_ctrl' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1546,53-1546,63) (VERI-1875) identifier 's_cpu_sus0' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1547,52-1547,61) (VERI-1875) identifier 's_int_sta' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1548,52-1548,61) (VERI-1875) identifier 's_int0_do' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1549,52-1549,65) (VERI-1875) identifier 'int0_mask_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1550,53-1550,63) (VERI-1875) identifier 's_cpu_sus1' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1551,52-1551,62) (VERI-1875) identifier 's_int1_sta' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1552,52-1552,61) (VERI-1875) identifier 's_int1_do' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1553,52-1553,65) (VERI-1875) identifier 'int1_mask_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1565,51-1565,65) (VERI-1875) identifier 'over_time_flag' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1565,72-1565,86) (VERI-1875) identifier 'fan_wdt_en_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1576,51-1576,66) (VERI-1875) identifier 'SI5332_CTRL_OUT' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1577,46-1577,62) (VERI-1875) identifier 'PRT_PRSNT_MODABS' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1578,46-1578,59) (VERI-1875) identifier 'PRT_INT_RXLOS' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1579,45-1579,59) (VERI-1875) identifier 'PRT_MDSL_TXFLT' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1580,45-1580,64) (VERI-1875) identifier 'prt_lpmod_txdis_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1583,51-1583,69) (VERI-1875) identifier 'front_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1584,51-1584,69) (VERI-1875) identifier 'alarm_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1588,51-1588,62) (VERI-1875) identifier 'thm_ctrl_en' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1597,45-1597,59) (VERI-1875) identifier 'overload_sta_r' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1607,51-1607,64) (VERI-1875) identifier 'fan_misc_ctrl' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1878,35-1878,53) (VERI-1875) identifier 'front_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1879,35-1879,53) (VERI-1875) identifier 'front_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1880,35-1880,53) (VERI-1875) identifier 'front_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1881,37-1881,55) (VERI-1875) identifier 'front_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1882,35-1882,53) (VERI-1875) identifier 'front_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1883,35-1883,53) (VERI-1875) identifier 'front_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1884,37-1884,55) (VERI-1875) identifier 'front_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1884,75-1884,93) (VERI-1875) identifier 'front_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1885,36-1885,54) (VERI-1875) identifier 'front_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1885,74-1885,92) (VERI-1875) identifier 'front_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1886,35-1886,53) (VERI-1875) identifier 'front_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1887,37-1887,55) (VERI-1875) identifier 'front_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1887,75-1887,93) (VERI-1875) identifier 'front_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1888,36-1888,54) (VERI-1875) identifier 'front_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1888,74-1888,92) (VERI-1875) identifier 'front_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1889,35-1889,53) (VERI-1875) identifier 'front_led_ctrl_reg' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1932,12-1932,24) (VERI-1875) identifier 'FAN1_PRESENT' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(2014,12-2014,24) (VERI-1875) identifier 'FAN2_PRESENT' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(2098,12-2098,24) (VERI-1875) identifier 'FAN3_PRESENT' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(2299,11-2299,19) (VERI-1875) identifier 'psu_ok_n' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(2316,11-2316,19) (VERI-1875) identifier 'psu_ok_n' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(2333,11-2333,19) (VERI-1875) identifier 'psu_ok_n' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(2540,28-2540,47) (VERI-1875) identifier 'prt_lpmod_txdis_reg' is used before its declaration
(VERI-1482) Analyzing Verilog file 'E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/cfg_int_gen.v'
(VERI-1482) Analyzing Verilog file 'E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/com_exp_ctrl.v'
(VERI-1482) Analyzing Verilog file 'E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/delay_mod.v'
(VERI-1482) Analyzing Verilog file 'E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/fan_ctrl.v'
(VERI-1482) Analyzing Verilog file 'E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/i2c_slave.v'
(VERI-1482) Analyzing Verilog file 'E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/LPC_IO_CYCLE.v'
(VERI-1482) Analyzing Verilog file 'E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/power_on_seq.v'
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/power_on_seq.v(341,7-341,21) (VERI-1372) redeclaration of ansi port 'power_off_flag' is not allowed
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/power_on_seq.v(373,6-373,28) (VERI-1372) redeclaration of ansi port 'pwr_en_0v8_avs' is not allowed
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/power_on_seq.v(196,16-196,32) (VERI-1875) identifier 'powr_off_sta_cnt' is used before its declaration
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/power_on_seq.v(204,19-204,27) (VERI-1875) identifier 'wait_cnt' is used before its declaration
(VERI-1482) Analyzing Verilog file 'E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/watchdog.v'
(VERI-1482) Analyzing Verilog file 'E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Wd_Ctrl.v'
INFO - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(18,8-18,26) (VERI-1018) compiling module 'Belgite_BOARD_CPLD'
INFO - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(18,1-2727,10) (VERI-9000) elaborating module 'Belgite_BOARD_CPLD'
INFO - E:/lattice 3.12/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793,1-1798,10) (VERI-9000) elaborating module 'OSCH_uniq_1'
INFO - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/i2c_slave.v(1,1-411,10) (VERI-9000) elaborating module 'i2c_slave_uniq_1'
INFO - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/LPC_IO_CYCLE.v(2,1-336,10) (VERI-9000) elaborating module 'LPC_IO_CYCLE_uniq_1'
INFO - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/power_on_seq.v(23,1-463,10) (VERI-9000) elaborating module 'power_on_seq_uniq_1'
INFO - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/com_exp_ctrl.v(2,1-672,10) (VERI-9000) elaborating module 'com_exp_ctrl_uniq_1'
INFO - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/watchdog.v(5,1-154,10) (VERI-9000) elaborating module 'watchdog_uniq_1'
INFO - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/cfg_int_gen.v(1,1-176,10) (VERI-9000) elaborating module 'cfg_int_gen_uniq_1'
INFO - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/cfg_int_gen.v(1,1-176,10) (VERI-9000) elaborating module 'cfg_int_gen_uniq_2'
INFO - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/fan_ctrl.v(1,1-168,10) (VERI-9000) elaborating module 'fan_ctrl_uniq_1'
INFO - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/fan_ctrl.v(1,1-168,10) (VERI-9000) elaborating module 'fan_ctrl_uniq_2'
INFO - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/fan_ctrl.v(1,1-168,10) (VERI-9000) elaborating module 'fan_ctrl_uniq_3'
INFO - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/delay_mod.v(1,1-27,10) (VERI-9000) elaborating module 'delay_mod_uniq_1'
INFO - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Wd_Ctrl.v(1,1-149,10) (VERI-9000) elaborating module 'Wd_Ctrl_uniq_1'
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(756,1-782,3) (VERI-1927) port 'pwr_en_0v8_avs' remains unconnected for this instance
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(948,1-973,3) (VERI-1927) port 'o_s_cp_cold_rst_flag' remains unconnected for this instance
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(1989,2-2005,4) (VERI-2435) port 'i_fan_led_ctrl' is not connected on this instance
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(2072,2-2089,4) (VERI-2435) port 'i_fan_led_ctrl' is not connected on this instance
WARNING - E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/source/Belgite_BOARD_CPLD.v(2156,2-2172,4) (VERI-2435) port 'i_fan_led_ctrl' is not connected on this instance
Done: design load finished with (0) errors, and (108) warnings