Place & Route TRACE Report
Loading design for application trce from file m0_cpld_v25_impl1.ncd.
Design name: Belgite_BOARD_CPLD
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-2000HC
Package: FTBGA256
Performance: 4
Loading device for application trce from file 'xo2c2000.nph' in environment: E:/lattice 3.12/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Mon Dec 06 18:58:17 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o M0_CPLD_V25_impl1.twr -gui -msgset E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/promote.xml M0_CPLD_V25_impl1.ncd M0_CPLD_V25_impl1.prf
Design file: m0_cpld_v25_impl1.ncd
Preference file: m0_cpld_v25_impl1.prf
Device,speed: LCMXO2-2000HC,4
Report level: verbose report, limited to 10 items per preference
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Preference Summary
FREQUENCY NET "clk_sys" 66.500000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
Report: 76.318MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY NET "clk_sys" 66.500000 MHz ;
4096 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 1.935ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_i2c_wr_dly[0] (from clk_sys +)
Destination: FF Data in clk_200ms_count_fan2[7] (to clk_sys +)
Delay: 12.937ns (38.8% logic, 61.2% route), 11 logic levels.
Constraint Details:
12.937ns physical path delay SLICE_524 to SLICE_162 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 1.935ns
Physical Path Details:
Data path SLICE_524 to SLICE_162:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R11C20B.CLK to R11C20B.Q0 SLICE_524 (from clk_sys)
ROUTE 6 2.005 R11C20B.Q0 to R6C18D.B1 s_i2c_wr_dly[0]
CTOF_DEL --- 0.495 R6C18D.B1 to R6C18D.F1 SLICE_841
ROUTE 11 0.996 R6C18D.F1 to R4C17B.D0 N_1913
CTOF_DEL --- 0.495 R4C17B.D0 to R4C17B.F0 SLICE_849
ROUTE 4 0.453 R4C17B.F0 to R4C17B.C1 N_4179
CTOF_DEL --- 0.495 R4C17B.C1 to R4C17B.F1 SLICE_849
ROUTE 5 1.088 R4C17B.F1 to R4C13B.D1 LPC_IO_Cycle_Inst/N_2178
CTOF_DEL --- 0.495 R4C13B.D1 to R4C13B.F1 SLICE_815
ROUTE 7 2.316 R4C13B.F1 to R13C6B.C0 N_1838
CTOF_DEL --- 0.495 R13C6B.C0 to R13C6B.F0 fan2_ctrl/SLICE_821
ROUTE 9 1.058 R13C6B.F0 to R13C5A.B0 N_2504_i
C0TOFCO_DE --- 1.023 R13C5A.B0 to R13C5A.FCO SLICE_166
ROUTE 1 0.000 R13C5A.FCO to R13C5B.FCI clk_200ms_count_fan2_cry[0]
FCITOFCO_D --- 0.162 R13C5B.FCI to R13C5B.FCO SLICE_165
ROUTE 1 0.000 R13C5B.FCO to R13C5C.FCI clk_200ms_count_fan2_cry[2]
FCITOFCO_D --- 0.162 R13C5C.FCI to R13C5C.FCO SLICE_164
ROUTE 1 0.000 R13C5C.FCO to R13C5D.FCI clk_200ms_count_fan2_cry[4]
FCITOFCO_D --- 0.162 R13C5D.FCI to R13C5D.FCO SLICE_163
ROUTE 1 0.000 R13C5D.FCO to R13C6A.FCI clk_200ms_count_fan2_cry[6]
FCITOF0_DE --- 0.585 R13C6A.FCI to R13C6A.F0 SLICE_162
ROUTE 1 0.000 R13C6A.F0 to R13C6A.DI0 clk_200ms_count_fan2_s[7] (to clk_sys)
--------
12.937 (38.8% logic, 61.2% route), 11 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_524:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R11C20B.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_162:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R13C6A.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.982ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_lpc_wr_dly[1] (from clk_sys +)
Destination: FF Data in clk_200ms_count_fan2[7] (to clk_sys +)
Delay: 12.890ns (35.1% logic, 64.9% route), 10 logic levels.
Constraint Details:
12.890ns physical path delay SLICE_526 to SLICE_162 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 1.982ns
Physical Path Details:
Data path SLICE_526 to SLICE_162:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C24D.CLK to R4C24D.Q1 SLICE_526 (from clk_sys)
ROUTE 5 1.940 R4C24D.Q1 to R6C16B.A1 s_lpc_wr_dly[1]
CTOF_DEL --- 0.495 R6C16B.A1 to R6C16B.F1 SLICE_843
ROUTE 18 1.336 R6C16B.F1 to R3C18B.C1 N_1854
CTOF_DEL --- 0.495 R3C18B.C1 to R3C18B.F1 SLICE_852
ROUTE 10 1.714 R3C18B.F1 to R4C13B.C1 LPC_IO_Cycle_Inst/N_3796
CTOF_DEL --- 0.495 R4C13B.C1 to R4C13B.F1 SLICE_815
ROUTE 7 2.316 R4C13B.F1 to R13C6B.C0 N_1838
CTOF_DEL --- 0.495 R13C6B.C0 to R13C6B.F0 fan2_ctrl/SLICE_821
ROUTE 9 1.058 R13C6B.F0 to R13C5A.B0 N_2504_i
C0TOFCO_DE --- 1.023 R13C5A.B0 to R13C5A.FCO SLICE_166
ROUTE 1 0.000 R13C5A.FCO to R13C5B.FCI clk_200ms_count_fan2_cry[0]
FCITOFCO_D --- 0.162 R13C5B.FCI to R13C5B.FCO SLICE_165
ROUTE 1 0.000 R13C5B.FCO to R13C5C.FCI clk_200ms_count_fan2_cry[2]
FCITOFCO_D --- 0.162 R13C5C.FCI to R13C5C.FCO SLICE_164
ROUTE 1 0.000 R13C5C.FCO to R13C5D.FCI clk_200ms_count_fan2_cry[4]
FCITOFCO_D --- 0.162 R13C5D.FCI to R13C5D.FCO SLICE_163
ROUTE 1 0.000 R13C5D.FCO to R13C6A.FCI clk_200ms_count_fan2_cry[6]
FCITOF0_DE --- 0.585 R13C6A.FCI to R13C6A.F0 SLICE_162
ROUTE 1 0.000 R13C6A.F0 to R13C6A.DI0 clk_200ms_count_fan2_s[7] (to clk_sys)
--------
12.890 (35.1% logic, 64.9% route), 10 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_526:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R4C24D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_162:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R13C6A.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 2.039ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_i2c_wr_dly[0] (from clk_sys +)
Destination: FF Data in clk_200ms_count_fan2[6] (to clk_sys +)
Delay: 12.833ns (38.3% logic, 61.7% route), 10 logic levels.
Constraint Details:
12.833ns physical path delay SLICE_524 to SLICE_163 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 2.039ns
Physical Path Details:
Data path SLICE_524 to SLICE_163:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R11C20B.CLK to R11C20B.Q0 SLICE_524 (from clk_sys)
ROUTE 6 2.005 R11C20B.Q0 to R6C18D.B1 s_i2c_wr_dly[0]
CTOF_DEL --- 0.495 R6C18D.B1 to R6C18D.F1 SLICE_841
ROUTE 11 0.996 R6C18D.F1 to R4C17B.D0 N_1913
CTOF_DEL --- 0.495 R4C17B.D0 to R4C17B.F0 SLICE_849
ROUTE 4 0.453 R4C17B.F0 to R4C17B.C1 N_4179
CTOF_DEL --- 0.495 R4C17B.C1 to R4C17B.F1 SLICE_849
ROUTE 5 1.088 R4C17B.F1 to R4C13B.D1 LPC_IO_Cycle_Inst/N_2178
CTOF_DEL --- 0.495 R4C13B.D1 to R4C13B.F1 SLICE_815
ROUTE 7 2.316 R4C13B.F1 to R13C6B.C0 N_1838
CTOF_DEL --- 0.495 R13C6B.C0 to R13C6B.F0 fan2_ctrl/SLICE_821
ROUTE 9 1.058 R13C6B.F0 to R13C5A.B0 N_2504_i
C0TOFCO_DE --- 1.023 R13C5A.B0 to R13C5A.FCO SLICE_166
ROUTE 1 0.000 R13C5A.FCO to R13C5B.FCI clk_200ms_count_fan2_cry[0]
FCITOFCO_D --- 0.162 R13C5B.FCI to R13C5B.FCO SLICE_165
ROUTE 1 0.000 R13C5B.FCO to R13C5C.FCI clk_200ms_count_fan2_cry[2]
FCITOFCO_D --- 0.162 R13C5C.FCI to R13C5C.FCO SLICE_164
ROUTE 1 0.000 R13C5C.FCO to R13C5D.FCI clk_200ms_count_fan2_cry[4]
FCITOF1_DE --- 0.643 R13C5D.FCI to R13C5D.F1 SLICE_163
ROUTE 1 0.000 R13C5D.F1 to R13C5D.DI1 clk_200ms_count_fan2_s[6] (to clk_sys)
--------
12.833 (38.3% logic, 61.7% route), 10 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_524:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R11C20B.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_163:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R13C5D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 2.069ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_i2c_wr_dly[0] (from clk_sys +)
Destination: FF Data in clk_200ms_count_fan2[7] (to clk_sys +)
Delay: 12.803ns (38.2% logic, 61.8% route), 11 logic levels.
Constraint Details:
12.803ns physical path delay SLICE_524 to SLICE_162 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 2.069ns
Physical Path Details:
Data path SLICE_524 to SLICE_162:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R11C20B.CLK to R11C20B.Q0 SLICE_524 (from clk_sys)
ROUTE 6 2.005 R11C20B.Q0 to R6C18D.B1 s_i2c_wr_dly[0]
CTOF_DEL --- 0.495 R6C18D.B1 to R6C18D.F1 SLICE_841
ROUTE 11 0.996 R6C18D.F1 to R4C17B.D0 N_1913
CTOF_DEL --- 0.495 R4C17B.D0 to R4C17B.F0 SLICE_849
ROUTE 4 0.453 R4C17B.F0 to R4C17B.C1 N_4179
CTOF_DEL --- 0.495 R4C17B.C1 to R4C17B.F1 SLICE_849
ROUTE 5 1.088 R4C17B.F1 to R4C13B.D1 LPC_IO_Cycle_Inst/N_2178
CTOF_DEL --- 0.495 R4C13B.D1 to R4C13B.F1 SLICE_815
ROUTE 7 2.316 R4C13B.F1 to R13C6B.C0 N_1838
CTOF_DEL --- 0.495 R13C6B.C0 to R13C6B.F0 fan2_ctrl/SLICE_821
ROUTE 9 1.058 R13C6B.F0 to R13C5A.B1 N_2504_i
C1TOFCO_DE --- 0.889 R13C5A.B1 to R13C5A.FCO SLICE_166
ROUTE 1 0.000 R13C5A.FCO to R13C5B.FCI clk_200ms_count_fan2_cry[0]
FCITOFCO_D --- 0.162 R13C5B.FCI to R13C5B.FCO SLICE_165
ROUTE 1 0.000 R13C5B.FCO to R13C5C.FCI clk_200ms_count_fan2_cry[2]
FCITOFCO_D --- 0.162 R13C5C.FCI to R13C5C.FCO SLICE_164
ROUTE 1 0.000 R13C5C.FCO to R13C5D.FCI clk_200ms_count_fan2_cry[4]
FCITOFCO_D --- 0.162 R13C5D.FCI to R13C5D.FCO SLICE_163
ROUTE 1 0.000 R13C5D.FCO to R13C6A.FCI clk_200ms_count_fan2_cry[6]
FCITOF0_DE --- 0.585 R13C6A.FCI to R13C6A.F0 SLICE_162
ROUTE 1 0.000 R13C6A.F0 to R13C6A.DI0 clk_200ms_count_fan2_s[7] (to clk_sys)
--------
12.803 (38.2% logic, 61.8% route), 11 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_524:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R11C20B.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_162:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R13C6A.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 2.086ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_lpc_wr_dly[1] (from clk_sys +)
Destination: FF Data in clk_200ms_count_fan2[6] (to clk_sys +)
Delay: 12.786ns (34.6% logic, 65.4% route), 9 logic levels.
Constraint Details:
12.786ns physical path delay SLICE_526 to SLICE_163 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 2.086ns
Physical Path Details:
Data path SLICE_526 to SLICE_163:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C24D.CLK to R4C24D.Q1 SLICE_526 (from clk_sys)
ROUTE 5 1.940 R4C24D.Q1 to R6C16B.A1 s_lpc_wr_dly[1]
CTOF_DEL --- 0.495 R6C16B.A1 to R6C16B.F1 SLICE_843
ROUTE 18 1.336 R6C16B.F1 to R3C18B.C1 N_1854
CTOF_DEL --- 0.495 R3C18B.C1 to R3C18B.F1 SLICE_852
ROUTE 10 1.714 R3C18B.F1 to R4C13B.C1 LPC_IO_Cycle_Inst/N_3796
CTOF_DEL --- 0.495 R4C13B.C1 to R4C13B.F1 SLICE_815
ROUTE 7 2.316 R4C13B.F1 to R13C6B.C0 N_1838
CTOF_DEL --- 0.495 R13C6B.C0 to R13C6B.F0 fan2_ctrl/SLICE_821
ROUTE 9 1.058 R13C6B.F0 to R13C5A.B0 N_2504_i
C0TOFCO_DE --- 1.023 R13C5A.B0 to R13C5A.FCO SLICE_166
ROUTE 1 0.000 R13C5A.FCO to R13C5B.FCI clk_200ms_count_fan2_cry[0]
FCITOFCO_D --- 0.162 R13C5B.FCI to R13C5B.FCO SLICE_165
ROUTE 1 0.000 R13C5B.FCO to R13C5C.FCI clk_200ms_count_fan2_cry[2]
FCITOFCO_D --- 0.162 R13C5C.FCI to R13C5C.FCO SLICE_164
ROUTE 1 0.000 R13C5C.FCO to R13C5D.FCI clk_200ms_count_fan2_cry[4]
FCITOF1_DE --- 0.643 R13C5D.FCI to R13C5D.F1 SLICE_163
ROUTE 1 0.000 R13C5D.F1 to R13C5D.DI1 clk_200ms_count_fan2_s[6] (to clk_sys)
--------
12.786 (34.6% logic, 65.4% route), 9 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_526:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R4C24D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_163:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R13C5D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 2.094ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q i2c_slave_inst0/o_ram_addr[7] (from clk_sys +)
Destination: FF Data in clk_200ms_count_fan2[7] (to clk_sys +)
Delay: 12.778ns (39.3% logic, 60.7% route), 11 logic levels.
Constraint Details:
12.778ns physical path delay SLICE_1034 to SLICE_162 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 2.094ns
Physical Path Details:
Data path SLICE_1034 to SLICE_162:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R12C18A.CLK to R12C18A.Q1 SLICE_1034 (from clk_sys)
ROUTE 15 1.846 R12C18A.Q1 to R6C18D.A1 s_i2c_addr[7]
CTOF_DEL --- 0.495 R6C18D.A1 to R6C18D.F1 SLICE_841
ROUTE 11 0.996 R6C18D.F1 to R4C17B.D0 N_1913
CTOF_DEL --- 0.495 R4C17B.D0 to R4C17B.F0 SLICE_849
ROUTE 4 0.453 R4C17B.F0 to R4C17B.C1 N_4179
CTOF_DEL --- 0.495 R4C17B.C1 to R4C17B.F1 SLICE_849
ROUTE 5 1.088 R4C17B.F1 to R4C13B.D1 LPC_IO_Cycle_Inst/N_2178
CTOF_DEL --- 0.495 R4C13B.D1 to R4C13B.F1 SLICE_815
ROUTE 7 2.316 R4C13B.F1 to R13C6B.C0 N_1838
CTOF_DEL --- 0.495 R13C6B.C0 to R13C6B.F0 fan2_ctrl/SLICE_821
ROUTE 9 1.058 R13C6B.F0 to R13C5A.B0 N_2504_i
C0TOFCO_DE --- 1.023 R13C5A.B0 to R13C5A.FCO SLICE_166
ROUTE 1 0.000 R13C5A.FCO to R13C5B.FCI clk_200ms_count_fan2_cry[0]
FCITOFCO_D --- 0.162 R13C5B.FCI to R13C5B.FCO SLICE_165
ROUTE 1 0.000 R13C5B.FCO to R13C5C.FCI clk_200ms_count_fan2_cry[2]
FCITOFCO_D --- 0.162 R13C5C.FCI to R13C5C.FCO SLICE_164
ROUTE 1 0.000 R13C5C.FCO to R13C5D.FCI clk_200ms_count_fan2_cry[4]
FCITOFCO_D --- 0.162 R13C5D.FCI to R13C5D.FCO SLICE_163
ROUTE 1 0.000 R13C5D.FCO to R13C6A.FCI clk_200ms_count_fan2_cry[6]
FCITOF0_DE --- 0.585 R13C6A.FCI to R13C6A.F0 SLICE_162
ROUTE 1 0.000 R13C6A.F0 to R13C6A.DI0 clk_200ms_count_fan2_s[7] (to clk_sys)
--------
12.778 (39.3% logic, 60.7% route), 11 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_1034:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R12C18A.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_162:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R13C6A.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 2.097ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_i2c_wr_dly[0] (from clk_sys +)
Destination: FF Data in clk_200ms_count_fan2[5] (to clk_sys +)
Delay: 12.775ns (38.0% logic, 62.0% route), 10 logic levels.
Constraint Details:
12.775ns physical path delay SLICE_524 to SLICE_163 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 2.097ns
Physical Path Details:
Data path SLICE_524 to SLICE_163:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R11C20B.CLK to R11C20B.Q0 SLICE_524 (from clk_sys)
ROUTE 6 2.005 R11C20B.Q0 to R6C18D.B1 s_i2c_wr_dly[0]
CTOF_DEL --- 0.495 R6C18D.B1 to R6C18D.F1 SLICE_841
ROUTE 11 0.996 R6C18D.F1 to R4C17B.D0 N_1913
CTOF_DEL --- 0.495 R4C17B.D0 to R4C17B.F0 SLICE_849
ROUTE 4 0.453 R4C17B.F0 to R4C17B.C1 N_4179
CTOF_DEL --- 0.495 R4C17B.C1 to R4C17B.F1 SLICE_849
ROUTE 5 1.088 R4C17B.F1 to R4C13B.D1 LPC_IO_Cycle_Inst/N_2178
CTOF_DEL --- 0.495 R4C13B.D1 to R4C13B.F1 SLICE_815
ROUTE 7 2.316 R4C13B.F1 to R13C6B.C0 N_1838
CTOF_DEL --- 0.495 R13C6B.C0 to R13C6B.F0 fan2_ctrl/SLICE_821
ROUTE 9 1.058 R13C6B.F0 to R13C5A.B0 N_2504_i
C0TOFCO_DE --- 1.023 R13C5A.B0 to R13C5A.FCO SLICE_166
ROUTE 1 0.000 R13C5A.FCO to R13C5B.FCI clk_200ms_count_fan2_cry[0]
FCITOFCO_D --- 0.162 R13C5B.FCI to R13C5B.FCO SLICE_165
ROUTE 1 0.000 R13C5B.FCO to R13C5C.FCI clk_200ms_count_fan2_cry[2]
FCITOFCO_D --- 0.162 R13C5C.FCI to R13C5C.FCO SLICE_164
ROUTE 1 0.000 R13C5C.FCO to R13C5D.FCI clk_200ms_count_fan2_cry[4]
FCITOF0_DE --- 0.585 R13C5D.FCI to R13C5D.F0 SLICE_163
ROUTE 1 0.000 R13C5D.F0 to R13C5D.DI0 clk_200ms_count_fan2_s[5] (to clk_sys)
--------
12.775 (38.0% logic, 62.0% route), 10 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_524:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R11C20B.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_163:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R13C5D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 2.116ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_lpc_wr_dly[1] (from clk_sys +)
Destination: FF Data in clk_200ms_count_fan2[7] (to clk_sys +)
Delay: 12.756ns (34.4% logic, 65.6% route), 10 logic levels.
Constraint Details:
12.756ns physical path delay SLICE_526 to SLICE_162 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 2.116ns
Physical Path Details:
Data path SLICE_526 to SLICE_162:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C24D.CLK to R4C24D.Q1 SLICE_526 (from clk_sys)
ROUTE 5 1.940 R4C24D.Q1 to R6C16B.A1 s_lpc_wr_dly[1]
CTOF_DEL --- 0.495 R6C16B.A1 to R6C16B.F1 SLICE_843
ROUTE 18 1.336 R6C16B.F1 to R3C18B.C1 N_1854
CTOF_DEL --- 0.495 R3C18B.C1 to R3C18B.F1 SLICE_852
ROUTE 10 1.714 R3C18B.F1 to R4C13B.C1 LPC_IO_Cycle_Inst/N_3796
CTOF_DEL --- 0.495 R4C13B.C1 to R4C13B.F1 SLICE_815
ROUTE 7 2.316 R4C13B.F1 to R13C6B.C0 N_1838
CTOF_DEL --- 0.495 R13C6B.C0 to R13C6B.F0 fan2_ctrl/SLICE_821
ROUTE 9 1.058 R13C6B.F0 to R13C5A.B1 N_2504_i
C1TOFCO_DE --- 0.889 R13C5A.B1 to R13C5A.FCO SLICE_166
ROUTE 1 0.000 R13C5A.FCO to R13C5B.FCI clk_200ms_count_fan2_cry[0]
FCITOFCO_D --- 0.162 R13C5B.FCI to R13C5B.FCO SLICE_165
ROUTE 1 0.000 R13C5B.FCO to R13C5C.FCI clk_200ms_count_fan2_cry[2]
FCITOFCO_D --- 0.162 R13C5C.FCI to R13C5C.FCO SLICE_164
ROUTE 1 0.000 R13C5C.FCO to R13C5D.FCI clk_200ms_count_fan2_cry[4]
FCITOFCO_D --- 0.162 R13C5D.FCI to R13C5D.FCO SLICE_163
ROUTE 1 0.000 R13C5D.FCO to R13C6A.FCI clk_200ms_count_fan2_cry[6]
FCITOF0_DE --- 0.585 R13C6A.FCI to R13C6A.F0 SLICE_162
ROUTE 1 0.000 R13C6A.F0 to R13C6A.DI0 clk_200ms_count_fan2_s[7] (to clk_sys)
--------
12.756 (34.4% logic, 65.6% route), 10 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_526:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R4C24D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_162:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R13C6A.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 2.134ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_i2c_wr_dly[0] (from clk_sys +)
Destination: FF Data in clk_200ms_count_fan2[7] (to clk_sys +)
Delay: 12.738ns (38.1% logic, 61.9% route), 10 logic levels.
Constraint Details:
12.738ns physical path delay SLICE_524 to SLICE_162 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 2.134ns
Physical Path Details:
Data path SLICE_524 to SLICE_162:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R11C20B.CLK to R11C20B.Q0 SLICE_524 (from clk_sys)
ROUTE 6 2.005 R11C20B.Q0 to R6C18D.B1 s_i2c_wr_dly[0]
CTOF_DEL --- 0.495 R6C18D.B1 to R6C18D.F1 SLICE_841
ROUTE 11 0.996 R6C18D.F1 to R4C17B.D0 N_1913
CTOF_DEL --- 0.495 R4C17B.D0 to R4C17B.F0 SLICE_849
ROUTE 4 0.453 R4C17B.F0 to R4C17B.C1 N_4179
CTOF_DEL --- 0.495 R4C17B.C1 to R4C17B.F1 SLICE_849
ROUTE 5 1.088 R4C17B.F1 to R4C13B.D1 LPC_IO_Cycle_Inst/N_2178
CTOF_DEL --- 0.495 R4C13B.D1 to R4C13B.F1 SLICE_815
ROUTE 7 2.316 R4C13B.F1 to R13C6B.C0 N_1838
CTOF_DEL --- 0.495 R13C6B.C0 to R13C6B.F0 fan2_ctrl/SLICE_821
ROUTE 9 1.021 R13C6B.F0 to R13C5B.A0 N_2504_i
C0TOFCO_DE --- 1.023 R13C5B.A0 to R13C5B.FCO SLICE_165
ROUTE 1 0.000 R13C5B.FCO to R13C5C.FCI clk_200ms_count_fan2_cry[2]
FCITOFCO_D --- 0.162 R13C5C.FCI to R13C5C.FCO SLICE_164
ROUTE 1 0.000 R13C5C.FCO to R13C5D.FCI clk_200ms_count_fan2_cry[4]
FCITOFCO_D --- 0.162 R13C5D.FCI to R13C5D.FCO SLICE_163
ROUTE 1 0.000 R13C5D.FCO to R13C6A.FCI clk_200ms_count_fan2_cry[6]
FCITOF0_DE --- 0.585 R13C6A.FCI to R13C6A.F0 SLICE_162
ROUTE 1 0.000 R13C6A.F0 to R13C6A.DI0 clk_200ms_count_fan2_s[7] (to clk_sys)
--------
12.738 (38.1% logic, 61.9% route), 10 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_524:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R11C20B.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_162:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R13C6A.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 2.144ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_lpc_wr_dly[1] (from clk_sys +)
Destination: FF Data in clk_200ms_count_fan2[5] (to clk_sys +)
Delay: 12.728ns (34.3% logic, 65.7% route), 9 logic levels.
Constraint Details:
12.728ns physical path delay SLICE_526 to SLICE_163 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 2.144ns
Physical Path Details:
Data path SLICE_526 to SLICE_163:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C24D.CLK to R4C24D.Q1 SLICE_526 (from clk_sys)
ROUTE 5 1.940 R4C24D.Q1 to R6C16B.A1 s_lpc_wr_dly[1]
CTOF_DEL --- 0.495 R6C16B.A1 to R6C16B.F1 SLICE_843
ROUTE 18 1.336 R6C16B.F1 to R3C18B.C1 N_1854
CTOF_DEL --- 0.495 R3C18B.C1 to R3C18B.F1 SLICE_852
ROUTE 10 1.714 R3C18B.F1 to R4C13B.C1 LPC_IO_Cycle_Inst/N_3796
CTOF_DEL --- 0.495 R4C13B.C1 to R4C13B.F1 SLICE_815
ROUTE 7 2.316 R4C13B.F1 to R13C6B.C0 N_1838
CTOF_DEL --- 0.495 R13C6B.C0 to R13C6B.F0 fan2_ctrl/SLICE_821
ROUTE 9 1.058 R13C6B.F0 to R13C5A.B0 N_2504_i
C0TOFCO_DE --- 1.023 R13C5A.B0 to R13C5A.FCO SLICE_166
ROUTE 1 0.000 R13C5A.FCO to R13C5B.FCI clk_200ms_count_fan2_cry[0]
FCITOFCO_D --- 0.162 R13C5B.FCI to R13C5B.FCO SLICE_165
ROUTE 1 0.000 R13C5B.FCO to R13C5C.FCI clk_200ms_count_fan2_cry[2]
FCITOFCO_D --- 0.162 R13C5C.FCI to R13C5C.FCO SLICE_164
ROUTE 1 0.000 R13C5C.FCO to R13C5D.FCI clk_200ms_count_fan2_cry[4]
FCITOF0_DE --- 0.585 R13C5D.FCI to R13C5D.F0 SLICE_163
ROUTE 1 0.000 R13C5D.F0 to R13C5D.DI0 clk_200ms_count_fan2_s[5] (to clk_sys)
--------
12.728 (34.3% logic, 65.7% route), 9 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_526:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R4C24D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_163:
Name Fanout Delay (ns) Site Resource
ROUTE 554 3.977 OSC.OSC to R13C5D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Report: 76.318MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_sys" 66.500000 MHz ; | 66.500 MHz| 76.318 MHz| 11
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: clk_sys Source: OSCH_inst.OSC Loads: 554
Covered under: FREQUENCY NET "clk_sys" 66.500000 MHz ;
Data transfers from:
Clock Domain: COME_CPLD_LPC_CLK_c Source: COME_CPLD_LPC_CLK.PAD
Not reported because source and destination domains are unrelated.
Clock Domain: COME_CPLD_LPC_CLK_c Source: COME_CPLD_LPC_CLK.PAD Loads: 29
No transfer within this clock domain is found
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 17586 paths, 1 nets, and 7071 connections (80.53% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
Mon Dec 06 18:58:17 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o M0_CPLD_V25_impl1.twr -gui -msgset E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/promote.xml M0_CPLD_V25_impl1.ncd M0_CPLD_V25_impl1.prf
Design file: m0_cpld_v25_impl1.ncd
Preference file: m0_cpld_v25_impl1.prf
Device,speed: LCMXO2-2000HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "clk_sys" 66.500000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "clk_sys" 66.500000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q i2c_slave_inst0/sr_r1[1] (from clk_sys +)
Destination: FF Data in i2c_slave_inst0/o_ram_di[1] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_1030 to SLICE_1140 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_1030 to SLICE_1140:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R10C13D.CLK to R10C13D.Q1 SLICE_1030 (from clk_sys)
ROUTE 1 0.152 R10C13D.Q1 to R10C13A.M1 i2c_slave_inst0/sr_r1[1] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_1030:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R10C13D.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_1140:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R10C13A.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q cb_rst_tmp[0] (from clk_sys +)
Destination: FF Data in cb_rst_tmp[1] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_1117 to SLICE_1117 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_1117 to SLICE_1117:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R6C5C.CLK to R6C5C.Q0 SLICE_1117 (from clk_sys)
ROUTE 1 0.152 R6C5C.Q0 to R6C5C.M1 cb_rst_tmp[0] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_1117:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R6C5C.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_1117:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R6C5C.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm75_int4_dly[0] (from clk_sys +)
Destination: FF Data in lm75_int4_dly[1] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_1135 to SLICE_1135 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_1135 to SLICE_1135:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R13C21D.CLK to R13C21D.Q0 SLICE_1135 (from clk_sys)
ROUTE 1 0.152 R13C21D.Q0 to R13C21D.M1 lm75_int4_dly[0] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_1135:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R13C21D.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_1135:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R13C21D.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q bios_sel_dly[0] (from clk_sys +)
Destination: FF Data in bios_sel_dly[1] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_265 to SLICE_265 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_265 to SLICE_265:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R11C5A.CLK to R11C5A.Q0 SLICE_265 (from clk_sys)
ROUTE 1 0.152 R11C5A.Q0 to R11C5A.M1 bios_sel_dly[0] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_265:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R11C5A.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_265:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R11C5A.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q com_exp_ctrl_inst1/pwrbtn_tri_r[0] (from clk_sys +)
Destination: FF Data in com_exp_ctrl_inst1/pwrbtn_tri_r[1] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_320 to SLICE_320 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_320 to SLICE_320:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_320 (from clk_sys)
ROUTE 1 0.152 R5C9D.Q0 to R5C9D.M1 com_exp_ctrl_inst1/pwrbtn_tri_r[0] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_320:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R5C9D.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_320:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R5C9D.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q i2c_slave_inst0/ram_clken_r4_0 (from clk_sys +)
Destination: FF Data in i2c_slave_inst0/ram_clken_r5 (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_437 to SLICE_441 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_437 to SLICE_441:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C18C.CLK to R7C18C.Q1 SLICE_437 (from clk_sys)
ROUTE 1 0.152 R7C18C.Q1 to R7C18D.M1 i2c_slave_inst0/ram_clken_r4_0 (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_437:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R7C18C.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_441:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R7C18D.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q psu_ok_r[0] (from clk_sys +)
Destination: FF Data in psu_ok_r[1] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_494 to SLICE_494 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_494 to SLICE_494:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C12A.CLK to R4C12A.Q0 SLICE_494 (from clk_sys)
ROUTE 1 0.152 R4C12A.Q0 to R4C12A.M1 psu_ok_r[0] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_494:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R4C12A.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_494:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R4C12A.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q u_watchdog/wd_punch_buf[1] (from clk_sys +)
Destination: FF Data in u_watchdog/wd_punch_buf[2] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_583 to SLICE_584 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_583 to SLICE_584:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C8B.CLK to R7C8B.Q1 SLICE_583 (from clk_sys)
ROUTE 1 0.152 R7C8B.Q1 to R7C8D.M0 u_watchdog/wd_punch_buf[1] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_583:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R7C8B.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_584:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R7C8D.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q u_watchdog/wd_punch_buf[2] (from clk_sys +)
Destination: FF Data in u_watchdog/wd_punch_buf[3] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_584 to SLICE_584 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_584 to SLICE_584:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C8D.CLK to R7C8D.Q0 SLICE_584 (from clk_sys)
ROUTE 1 0.152 R7C8D.Q0 to R7C8D.M1 u_watchdog/wd_punch_buf[2] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_584:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R7C8D.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_584:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R7C8D.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q u_watchdog/Wd_Ctrl_Inst/s_next_sta[3] (from clk_sys +)
Destination: FF Data in u_watchdog/Wd_Ctrl_Inst/s_current_sta[3] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay u_watchdog/Wd_Ctrl_Inst/SLICE_566 to u_watchdog/Wd_Ctrl_Inst/SLICE_1023 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path u_watchdog/Wd_Ctrl_Inst/SLICE_566 to u_watchdog/Wd_Ctrl_Inst/SLICE_1023:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R12C17D.CLK to R12C17D.Q1 u_watchdog/Wd_Ctrl_Inst/SLICE_566 (from clk_sys)
ROUTE 1 0.152 R12C17D.Q1 to R12C17B.M1 u_watchdog/Wd_Ctrl_Inst/s_next_sta[3] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to u_watchdog/Wd_Ctrl_Inst/SLICE_566:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R12C17D.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to u_watchdog/Wd_Ctrl_Inst/SLICE_1023:
Name Fanout Delay (ns) Site Resource
ROUTE 554 1.416 OSC.OSC to R12C17B.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_sys" 66.500000 MHz ; | 0.000 ns| 0.304 ns| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: clk_sys Source: OSCH_inst.OSC Loads: 554
Covered under: FREQUENCY NET "clk_sys" 66.500000 MHz ;
Data transfers from:
Clock Domain: COME_CPLD_LPC_CLK_c Source: COME_CPLD_LPC_CLK.PAD
Not reported because source and destination domains are unrelated.
Clock Domain: COME_CPLD_LPC_CLK_c Source: COME_CPLD_LPC_CLK.PAD Loads: 29
No transfer within this clock domain is found
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 17586 paths, 1 nets, and 7071 connections (80.53% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
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