Map TRACE Report
Loading design for application trce from file m0_cpld_v25_impl1_map.ncd.
Design name: Belgite_BOARD_CPLD
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-2000HC
Package: FTBGA256
Performance: 4
Loading device for application trce from file 'xo2c2000.nph' in environment: E:/lattice 3.12/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Mon Dec 06 18:57:41 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o M0_CPLD_V25_impl1.tw1 -gui -msgset E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/promote.xml M0_CPLD_V25_impl1_map.ncd M0_CPLD_V25_impl1.prf
Design file: m0_cpld_v25_impl1_map.ncd
Preference file: m0_cpld_v25_impl1.prf
Device,speed: LCMXO2-2000HC,4
Report level: verbose report, limited to 1 item per preference
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Preference Summary
FREQUENCY NET "clk_sys" 66.500000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
Report: 74.538MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY NET "clk_sys" 66.500000 MHz ;
4096 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 1.622ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm75_int4_thm (from clk_sys +)
Destination: FF Data in lpc_data_i[3] (to clk_sys +)
Delay: 13.250ns (34.8% logic, 65.2% route), 9 logic levels.
Constraint Details:
13.250ns physical path delay SLICE_450 to SLICE_457 meets
15.038ns delay constraint less
0.166ns DIN_SET requirement (totaling 14.872ns) by 1.622ns
Physical Path Details:
Data path SLICE_450 to SLICE_457:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 SLICE_450.CLK to SLICE_450.Q0 SLICE_450 (from clk_sys)
ROUTE 2 e 1.234 SLICE_450.Q0 to SLICE_887.A1 lm75_int4_thm
CTOF_DEL --- 0.495 SLICE_887.A1 to SLICE_887.F1 SLICE_887
ROUTE 4 e 1.234 SLICE_887.F1 to SLICE_893.A0 u_power_seq/N_2003
CTOF_DEL --- 0.495 SLICE_893.A0 to SLICE_893.F0 SLICE_893
ROUTE 4 e 1.234 SLICE_893.F0 to *SLICE_1055.B0 PWR2_XP1R8V_EN_0_o3_0_o3_i_m3
CTOF_DEL --- 0.495 *SLICE_1055.B0 to *SLICE_1055.F0 LPC_IO_Cycle_Inst/SLICE_1055
ROUTE 1 e 1.234 *SLICE_1055.F0 to */SLICE_654.D1 LPC_IO_Cycle_Inst/N_1348
CTOOFX_DEL --- 0.721 */SLICE_654.D1 to *LICE_654.OFX0 LPC_IO_Cycle_Inst/lpc_data_i_72_22[3]/SLICE_654
ROUTE 1 e 1.234 *LICE_654.OFX0 to *SLICE_1124.A0 LPC_IO_Cycle_Inst/N_1364
CTOF_DEL --- 0.495 *SLICE_1124.A0 to *SLICE_1124.F0 LPC_IO_Cycle_Inst/SLICE_1124
ROUTE 1 e 1.234 *SLICE_1124.F0 to */SLICE_627.B0 LPC_IO_Cycle_Inst/N_1428
CTOOFX_DEL --- 0.721 */SLICE_627.B0 to *LICE_627.OFX0 LPC_IO_Cycle_Inst/lpc_data_i_72_60[3]/SLICE_627
ROUTE 1 e 0.001 *LICE_627.OFX0 to *SLICE_641.FXA LPC_IO_Cycle_Inst/N_1668
FXTOOFX_DE --- 0.241 *SLICE_641.FXA to *LICE_641.OFX1 LPC_IO_Cycle_Inst/lpc_data_i_72_96[3]/SLICE_641
ROUTE 1 e 1.234 *LICE_641.OFX1 to SLICE_457.A1 LPC_IO_Cycle_Inst/N_1964
CTOF_DEL --- 0.495 SLICE_457.A1 to SLICE_457.F1 SLICE_457
ROUTE 1 e 0.001 SLICE_457.F1 to SLICE_457.DI1 lpc_data_i_72[3] (to clk_sys)
--------
13.250 (34.8% logic, 65.2% route), 9 logic levels.
Report: 74.538MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_sys" 66.500000 MHz ; | 66.500 MHz| 74.538 MHz| 9
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: clk_sys Source: OSCH_inst.OSC Loads: 554
Covered under: FREQUENCY NET "clk_sys" 66.500000 MHz ;
Data transfers from:
Clock Domain: COME_CPLD_LPC_CLK_c Source: COME_CPLD_LPC_CLK.PAD
Not reported because source and destination domains are unrelated.
Clock Domain: COME_CPLD_LPC_CLK_c Source: COME_CPLD_LPC_CLK.PAD Loads: 29
No transfer within this clock domain is found
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 17586 paths, 1 nets, and 7071 connections (80.53% coverage)
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Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
Mon Dec 06 18:57:42 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o M0_CPLD_V25_impl1.tw1 -gui -msgset E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_bb/promote.xml M0_CPLD_V25_impl1_map.ncd M0_CPLD_V25_impl1.prf
Design file: m0_cpld_v25_impl1_map.ncd
Preference file: m0_cpld_v25_impl1.prf
Device,speed: LCMXO2-2000HC,M
Report level: verbose report, limited to 1 item per preference
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Preference Summary
FREQUENCY NET "clk_sys" 66.500000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "clk_sys" 66.500000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.351ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q U_INT0/loop[0].int_status_r1[0] (from clk_sys +)
Destination: FF Data in U_INT0/loop[0].int_status_r2[0] (to clk_sys +)
Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
Constraint Details:
0.332ns physical path delay SLICE_1019 to SLICE_1019 meets
-0.019ns M_HLD and
0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
Physical Path Details:
Data path SLICE_1019 to SLICE_1019:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 SLICE_1019.CLK to SLICE_1019.Q0 SLICE_1019 (from clk_sys)
ROUTE 2 e 0.199 SLICE_1019.Q0 to SLICE_1019.M1 U_INT0/int_status_r1[0] (to clk_sys)
--------
0.332 (40.1% logic, 59.9% route), 1 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_sys" 66.500000 MHz ; | 0.000 ns| 0.351 ns| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: clk_sys Source: OSCH_inst.OSC Loads: 554
Covered under: FREQUENCY NET "clk_sys" 66.500000 MHz ;
Data transfers from:
Clock Domain: COME_CPLD_LPC_CLK_c Source: COME_CPLD_LPC_CLK.PAD
Not reported because source and destination domains are unrelated.
Clock Domain: COME_CPLD_LPC_CLK_c Source: COME_CPLD_LPC_CLK.PAD Loads: 29
No transfer within this clock domain is found
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 17586 paths, 1 nets, and 7071 connections (80.53% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
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