Synthesis Report
#Build: Synplify Pro (R) Q-2020.03L-SP1, Build 182R, Oct 29 2020
#install: E:\lattice 3.12\diamond\3.12\synpbase
#OS: Windows 8 6.2
#Hostname: HP-PC
# Mon Dec 6 18:57:02 2021
#Implementation: impl1
Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03L-SP1
Install: E:\lattice 3.12\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: HP-PC
Implementation : impl1
Synopsys HDL Compiler, Version comp202003synp2, Build 182R, Built Oct 29 2020 10:49:53, @
@N|Running in 64-bit mode
###########################################################[
Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03L-SP1
Install: E:\lattice 3.12\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: HP-PC
Implementation : impl1
Synopsys Verilog Compiler, Version comp202003synp2, Build 182R, Built Oct 29 2020 10:49:53, @
@N|Running in 64-bit mode
@I::"E:\lattice 3.12\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
@I::"E:\lattice 3.12\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"E:\lattice 3.12\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"E:\lattice 3.12\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"E:\lattice 3.12\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"E:\lattice 3.12\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v" (library work)
@N: CG334 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":15:13:15:25|Read directive translate_off.
@N: CG333 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":17:13:17:24|Read directive translate_on.
@W: CG921 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":755:13:755:16|led2 is already declared in this scope.
@W: CG1249 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":974:22:974:37|Redeclaration of implicit signal com_exp_ctrl_sta
@W: CG1249 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1662:20:1662:32|Redeclaration of implicit signal thm_shutdwn_n
@W: CG921 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1873:15:1873:30|sysled_green_tem is already declared in this scope.
@W: CG921 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1874:15:1874:30|sysled_amber_tem is already declared in this scope.
@W: CG921 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1908:28:1908:44|come_pwr_ctrl_reg is already declared in this scope.
@W: CG1249 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2229:14:2229:25|Redeclaration of implicit signal fan1_pwm_out
@W: CG1249 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2230:14:2230:25|Redeclaration of implicit signal fan2_pwm_out
@W: CG1249 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2231:14:2231:25|Redeclaration of implicit signal fan3_pwm_out
@W: CG1337 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2540:9:2540:22|Net PRT_LPMD_TXDIS is not declared.
@W: CG1337 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2710:9:2710:24|Net IPROC_LED1_CLK_C is not declared.
@W: CG1337 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2711:9:2711:25|Net IPROC_LED1_DATA_C is not declared.
@W: CG1337 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2725:8:2725:24|Net o_tpm_lpc_reset_n is not declared.
@I::"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\cfg_int_gen.v" (library work)
@I::"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v" (library work)
@I::"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\delay_mod.v" (library work)
@I::"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\fan_ctrl.v" (library work)
@I::"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\i2c_slave.v" (library work)
@I::"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\LPC_IO_CYCLE.v" (library work)
@I::"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v" (library work)
@W: CG921 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":341:6:341:19|power_off_flag is already declared in this scope.
@W: CG921 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":373:5:373:18|pwr_en_0v8_avs is already declared in this scope.
@I::"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\watchdog.v" (library work)
@N: CG334 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\watchdog.v":1:13:1:25|Read directive translate_off.
@N: CG333 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\watchdog.v":3:13:3:24|Read directive translate_on.
@I::"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Wd_Ctrl.v" (library work)
Verilog syntax check successful!
Selecting top level module Belgite_BOARD_CPLD
@N: CG364 :"E:\lattice 3.12\diamond\3.12\synpbase\lib\lucent\machxo2.v":1793:7:1793:10|Synthesizing module OSCH in library work.
Running optimization stage 1 on OSCH .......
@N: CG364 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\i2c_slave.v":1:7:1:15|Synthesizing module i2c_slave in library work.
I2C_ADR=7'b0110010
idle=8'b00000001
start=8'b00000010
slave_addr=8'b00000100
slave_addr_ack=8'b00001000
mem_addr=8'b00010000
mem_addr_ack=8'b00100000
data=8'b01000000
data_ack=8'b10000000
Generated name = i2c_slave_50_1_2_4_8_16_32_64_128
Running optimization stage 1 on i2c_slave_50_1_2_4_8_16_32_64_128 .......
@N: CG364 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\LPC_IO_CYCLE.v":2:7:2:18|Synthesizing module LPC_IO_CYCLE in library work.
IO_RANGE_LOW=12'b101000010000
IO_RANGE_HIGH=12'b101000011111
IDLE=6'b000001
START=6'b000010
CTDIR=6'b000100
ADDR=6'b001000
RDATA=6'b010000
WDATA=6'b100000
MEM_RD=4'b0100
MEM_WR=4'b0110
IO_RD=4'b0000
IO_WR=4'b0010
Generated name = LPC_IO_CYCLE_Z1
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\LPC_IO_CYCLE.v":78:35:78:49|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\LPC_IO_CYCLE.v":95:35:95:49|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\LPC_IO_CYCLE.v":112:36:112:51|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\LPC_IO_CYCLE.v":129:28:129:35|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\LPC_IO_CYCLE.v":210:29:210:37|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\LPC_IO_CYCLE.v":326:18:326:25|Removing redundant assignment.
Running optimization stage 1 on LPC_IO_CYCLE_Z1 .......
@N: CG364 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":23:7:23:18|Synthesizing module power_on_seq in library work.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":332:22:332:29|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":352:29:352:44|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":356:29:356:44|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":445:27:445:43|Removing redundant assignment.
@W: CG360 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":53:24:53:37|Removing wire SYS_CB_1R0V_PG, as there is no assignment to it.
@W: CG360 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":54:24:54:37|Removing wire SYS_CB_3R3V_PG, as there is no assignment to it.
@W: CG360 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":57:24:57:27|Removing wire led2, as there is no assignment to it.
@W: CG360 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":58:24:58:39|Removing wire curr_state_debug, as there is no assignment to it.
@W: CG360 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":97:6:97:19|Removing wire delay_done_3v3, as there is no assignment to it.
@W: CG360 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":98:6:98:19|Removing wire delay_done_1v0, as there is no assignment to it.
@W: CG360 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":99:6:99:23|Removing wire delay_done_0v8_avs, as there is no assignment to it.
Running optimization stage 1 on power_on_seq .......
@W: CL318 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":53:24:53:37|*Output SYS_CB_1R0V_PG has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":54:24:54:37|*Output SYS_CB_3R3V_PG has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":57:24:57:27|*Output led2 has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":58:24:58:39|*Output curr_state_debug has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@N: CG364 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\delay_mod.v":1:7:1:15|Synthesizing module delay_mod in library work.
Running optimization stage 1 on delay_mod .......
@N: CG364 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":2:7:2:18|Synthesizing module com_exp_ctrl in library work.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":298:35:298:45|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":324:40:324:51|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":355:25:355:38|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":370:39:370:49|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":387:39:387:49|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":404:39:404:49|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":420:30:420:43|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":437:26:437:37|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":488:39:488:49|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":502:29:502:41|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":523:44:523:59|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":546:43:546:57|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":568:35:568:42|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":573:28:573:35|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":588:28:588:39|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":598:28:598:39|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":612:37:612:45|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":615:29:615:37|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":638:43:638:57|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":660:44:660:59|Removing redundant assignment.
@W: CG360 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":67:15:67:28|Removing wire en_12v_cpu_dly, as there is no assignment to it.
Running optimization stage 1 on com_exp_ctrl .......
@W: CL168 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":665:14:665:29|Removing instance inst_pwrgd_stby5 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL169 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":308:4:308:9|Pruning unused register cpu_s5_count[2:0]. Make sure that there are no unused intermediate registers.
@N: CG364 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Wd_Ctrl.v":1:7:1:13|Synthesizing module Wd_Ctrl in library work.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Wd_Ctrl.v":85:16:85:24|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Wd_Ctrl.v":137:19:137:30|Removing redundant assignment.
Running optimization stage 1 on Wd_Ctrl .......
@N: CG364 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\watchdog.v":5:7:5:14|Synthesizing module watchdog in library work.
WD_SET_TIMER_H=8'b01100001
WD_SET_TIMER_M=8'b01100010
WD_SET_TIMER_L=8'b01100011
WD_USE_TIMER_H=8'b01100100
WD_USE_TIMER_M=8'b01100101
WD_USE_TIMER_L=8'b01100110
WD_EN=8'b01100111
WD_FEED=8'b01101000
WD_PUNCH=8'b01101001
Generated name = watchdog_97_98_99_100_101_102_103_104_105
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\watchdog.v":48:21:48:34|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\watchdog.v":60:21:60:34|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\watchdog.v":72:21:72:34|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\watchdog.v":86:12:86:16|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\watchdog.v":129:14:129:20|Removing redundant assignment.
Running optimization stage 1 on watchdog_97_98_99_100_101_102_103_104_105 .......
@N: CG364 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\cfg_int_gen.v":1:7:1:17|Synthesizing module cfg_int_gen in library work.
DI_WIDTH=4'b0110
Generated name = cfg_int_gen_6
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\cfg_int_gen.v":87:30:87:45|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\cfg_int_gen.v":102:29:102:44|Removing redundant assignment.
Running optimization stage 1 on cfg_int_gen_6 .......
@N: CG364 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\cfg_int_gen.v":1:7:1:17|Synthesizing module cfg_int_gen in library work.
DI_WIDTH=4'b0100
Generated name = cfg_int_gen_4
Running optimization stage 1 on cfg_int_gen_4 .......
@N: CG364 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\fan_ctrl.v":1:7:1:14|Synthesizing module fan_ctrl in library work.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\fan_ctrl.v":100:32:100:49|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\fan_ctrl.v":122:36:122:51|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\fan_ctrl.v":150:30:150:45|Removing redundant assignment.
Running optimization stage 1 on fan_ctrl .......
@N: CG364 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":18:7:18:24|Synthesizing module Belgite_BOARD_CPLD in library work.
@W: CG532 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":337:1:337:7|Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored. Simulation mismatch may occur
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":343:23:343:38|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":397:22:397:33|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":424:27:424:44|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":451:25:451:39|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":478:25:478:39|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":688:26:688:41|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":706:24:706:37|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":880:20:880:32|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":892:23:892:35|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":899:23:899:35|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":902:20:902:32|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1096:24:1096:35|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1102:19:1102:30|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1189:24:1189:40|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1256:20:1256:32|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1284:19:1284:30|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1318:18:1318:28|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1338:17:1338:26|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1380:26:1380:41|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1520:20:1520:31|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1618:18:1618:27|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1673:23:1673:35|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1685:23:1685:35|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1688:20:1688:32|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1849:23:1849:35|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1866:23:1866:35|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1944:29:1944:48|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1970:28:1970:43|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1976:23:1976:38|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2026:29:2026:48|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2053:28:2053:43|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2059:23:2059:38|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2110:29:2110:48|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2137:28:2137:43|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2143:23:2143:38|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2189:21:2189:31|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2198:19:2198:29|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2199:20:2199:31|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2273:22:2273:29|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2469:16:2469:23|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2484:16:2484:23|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2591:23:2591:36|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2660:18:2660:24|Removing redundant assignment.
@W: CG1340 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2676:28:2676:39|Index into variable led_data could be out of range ; a simulation mismatch is possible.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2696:23:2696:35|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2705:21:2705:33|Removing redundant assignment.
@N: CG179 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2706:22:2706:35|Removing redundant assignment.
@W: CG781 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1989:10:1989:18|Input i_fan_led_ctrl on instance fan1_ctrl is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2072:10:2072:18|Input i_fan_led_ctrl on instance fan2_ctrl is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2156:10:2156:18|Input i_fan_led_ctrl on instance fan3_ctrl is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG360 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":166:24:166:36|Removing wire R_TPM_LPCPD_L, as there is no assignment to it.
Running optimization stage 1 on Belgite_BOARD_CPLD .......
@W: CL318 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":166:24:166:36|*Output R_TPM_LPCPD_L has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@W: CL169 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1342:1:1342:6|Pruning unused register cp_cold_rst_flag. Make sure that there are no unused intermediate registers.
@W: CL271 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2504:1:2504:6|Pruning unused bits 7 to 5 of psu_force_ctrl[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2504:1:2504:6|Pruning unused bits 3 to 2 of psu_force_ctrl[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL265 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2118:1:2118:6|Removing unused bit 2 of fan3_tach_dly[2:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2034:1:2034:6|Removing unused bit 2 of fan2_tach_dly[2:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1952:1:1952:6|Removing unused bit 2 of fan1_tach_dly[2:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1238:1:1238:6|Removing unused bit 2 of power_cycle_dly[2:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1230:1:1230:6|Removing unused bit 2 of cb_sus_s3[2:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1222:1:1222:6|Removing unused bit 2 of pwr_btn_r[2:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1167:1:1167:6|Removing unused bit 2 of watch_dog_rst_r[2:0]. Either assign all bits or reduce the width of the signal.
@W: CL113 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|Feedback mux created for signal led_data[15:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL251 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[15] assign 1, register removed by optimization
@W: CL250 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[14] assign 0, register removed by optimization
@W: CL251 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[13] assign 1, register removed by optimization
@W: CL250 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[12] assign 0, register removed by optimization
@W: CL251 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[11] assign 1, register removed by optimization
@W: CL250 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[10] assign 0, register removed by optimization
@W: CL251 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[9] assign 1, register removed by optimization
@W: CL250 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[8] assign 0, register removed by optimization
@W: CL251 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[7] assign 1, register removed by optimization
@W: CL250 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[6] assign 0, register removed by optimization
@W: CL251 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[5] assign 1, register removed by optimization
@W: CL250 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[4] assign 0, register removed by optimization
@W: CL251 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[3] assign 1, register removed by optimization
@W: CL250 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[2] assign 0, register removed by optimization
@W: CL251 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[1] assign 1, register removed by optimization
@W: CL250 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2665:1:2665:6|All reachable assignments to led_data[0] assign 0, register removed by optimization
Running optimization stage 2 on Belgite_BOARD_CPLD .......
@N: CL189 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":338:1:338:6|Register bit internal_por_cnt[5] is always 1.
@W: CL190 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1959:1:1959:6|Optimizing register bit FAN1_PRESENT_CNT[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2042:1:2042:6|Optimizing register bit FAN2_PRESENT_CNT[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2126:1:2126:6|Optimizing register bit FAN3_PRESENT_CNT[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":605:1:605:6|Optimizing register bit sw_rst_cnt[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":605:1:605:6|Optimizing register bit sw_rst_cnt[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":605:1:605:6|Pruning register bits 10 to 9 of sw_rst_cnt[10:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2126:1:2126:6|Pruning register bit 2 of FAN3_PRESENT_CNT[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":2042:1:2042:6|Pruning register bit 2 of FAN2_PRESENT_CNT[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":1959:1:1959:6|Pruning register bit 2 of FAN1_PRESENT_CNT[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":338:1:338:6|Pruning register bit 5 of internal_por_cnt[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N: CL159 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\Belgite_BOARD_CPLD.v":69:24:69:36|Input CB_THRMTRIP_N is unused.
Running optimization stage 2 on fan_ctrl .......
@N: CL159 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\fan_ctrl.v":13:26:13:39|Input i_fan_led_ctrl is unused.
Running optimization stage 2 on cfg_int_gen_4 .......
Running optimization stage 2 on cfg_int_gen_6 .......
Running optimization stage 2 on watchdog_97_98_99_100_101_102_103_104_105 .......
@W: CL246 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\watchdog.v":20:24:20:36|Input port bits 15 to 8 of lpc_data_addr[15:0] are unused. Assign logic for all port bits or change the input port size.
Running optimization stage 2 on Wd_Ctrl .......
Running optimization stage 2 on com_exp_ctrl .......
@W: CL190 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":553:4:553:9|Optimizing register bit boot_cnt[10] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":553:4:553:9|Optimizing register bit boot_cnt[11] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":553:4:553:9|Pruning register bits 11 to 10 of boot_cnt[11:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N: CL201 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\com_exp_ctrl.v":111:4:111:9|Trying to extract state machine for register current_sta.
Extracted state machine for register current_sta
State machine has 10 reachable states with original encodings of:
0000000001
0000000010
0000000100
0000001000
0000010000
0000100000
0001000000
0010000000
0100000000
1000000000
Running optimization stage 2 on delay_mod .......
Running optimization stage 2 on power_on_seq .......
@W: CL190 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":287:1:287:6|Optimizing register bit delay_cnt_1v8_1v2_0v8[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":287:1:287:6|Optimizing register bit delay_cnt_1v8_1v2_0v8[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":287:1:287:6|Pruning register bits 3 to 2 of delay_cnt_1v8_1v2_0v8[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N: CL201 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":89:1:89:6|Trying to extract state machine for register C_State.
Extracted state machine for register C_State
State machine has 9 reachable states with original encodings of:
0000
0101
0110
0111
1000
1001
1010
1011
1100
@W: CL249 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\power_on_seq.v":89:1:89:6|Initial value is not supported on state machine C_State
Running optimization stage 2 on LPC_IO_CYCLE_Z1 .......
@N: CL201 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\LPC_IO_CYCLE.v":134:4:134:9|Trying to extract state machine for register cur_state.
Extracted state machine for register cur_state
State machine has 6 reachable states with original encodings of:
000001
000010
000100
001000
010000
100000
Running optimization stage 2 on i2c_slave_50_1_2_4_8_16_32_64_128 .......
@N: CL135 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\i2c_slave.v":78:0:78:5|Found sequential shift ram_clken_r10 with address depth of 4 words and data bit width of 1.
@N: CL135 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\i2c_slave.v":78:0:78:5|Found sequential shift ram_clken_r6 with address depth of 3 words and data bit width of 1.
@N: CL201 :"E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\source\i2c_slave.v":279:0:279:5|Trying to extract state machine for register cs.
Extracted state machine for register cs
State machine has 8 reachable states with original encodings of:
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000
Running optimization stage 2 on OSCH .......
For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\impl1\synwork\layer0.rt.csv
At c_ver Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 112MB peak: 124MB)
Process took 0h:00m:04s realtime, 0h:00m:04s cputime
Process completed successfully.
# Mon Dec 6 18:57:07 2021
###########################################################]
###########################################################[
Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03L-SP1
Install: E:\lattice 3.12\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: HP-PC
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 182R, Built Oct 29 2020 10:49:53, @
@N|Running in 64-bit mode
File E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\impl1\synwork\layer0.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 94MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Mon Dec 6 18:57:08 2021
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\impl1\synwork\M0_CPLD_V25_impl1_comp.rt.csv
@END
At c_hdl Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 23MB peak: 23MB)
Process took 0h:00m:05s realtime, 0h:00m:05s cputime
Process completed successfully.
# Mon Dec 6 18:57:08 2021
###########################################################]
###########################################################[
Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03L-SP1
Install: E:\lattice 3.12\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: HP-PC
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 182R, Built Oct 29 2020 10:49:53, @
@N|Running in 64-bit mode
File E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\impl1\synwork\M0_CPLD_V25_impl1_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Mon Dec 6 18:57:09 2021
###########################################################]
# Mon Dec 6 18:57:10 2021
Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03L-SP1
Install: E:\lattice 3.12\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: HP-PC
Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version map202003lat, Build 172R, Built Nov 2 2020 09:31:45, @
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
@A: MF827 |No constraint file specified.
@L: E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\impl1\M0_CPLD_V25_impl1_scck.rpt
See clock summary report "E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\impl1\M0_CPLD_V25_impl1_scck.rpt"
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 129MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 130MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 141MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
@N: FX493 |Applying initial value "0" on instance pwr_en_0v8_avs.
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@N: FX493 |Applying initial value "0" on instance pwr_en_1v0.
@N: FX493 |Applying initial value "0" on instance pwr_en_0v8.
@N: FX493 |Applying initial value "0" on instance pwr_en_1v2.
@N: FX493 |Applying initial value "0" on instance pwr_en_1v8.
@N: FX493 |Applying initial value "0" on instance pwr_en_3v3_mdio.
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\power_on_seq.v":400:1:400:6|Removing sequential instance u_power_seq.pwr_en_3v3_mdio because it is equivalent to instance u_power_seq.pwr_en_1v8. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\power_on_seq.v":400:1:400:6|Removing sequential instance u_power_seq.pwr_en_1v8 because it is equivalent to instance u_power_seq.pwr_en_1v2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\power_on_seq.v":400:1:400:6|Removing sequential instance u_power_seq.pwr_en_1v2 because it is equivalent to instance u_power_seq.pwr_en_0v8. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\power_on_seq.v":386:1:386:6|Removing sequential instance u_power_seq.pwr_en_0v8_avs because it is equivalent to instance u_power_seq.pwr_en_1v0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\com_exp_ctrl.v":621:4:621:9|Removing sequential instance com_exp_ctrl_inst1.o_com_5v_enable because it is equivalent to instance com_exp_ctrl_inst1.o_com_12v_enable. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\power_on_seq.v":53:24:53:37|Tristate driver SYS_CB_1R0V_PG (in view: work.power_on_seq(verilog)) on net SYS_CB_1R0V_PG (in view: work.power_on_seq(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\power_on_seq.v":54:24:54:37|Tristate driver SYS_CB_3R3V_PG (in view: work.power_on_seq(verilog)) on net SYS_CB_3R3V_PG (in view: work.power_on_seq(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\power_on_seq.v":58:24:58:39|Tristate driver curr_state_debug_1 (in view: work.power_on_seq(verilog)) on net curr_state_debug_1 (in view: work.power_on_seq(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\power_on_seq.v":58:24:58:39|Tristate driver curr_state_debug_2 (in view: work.power_on_seq(verilog)) on net curr_state_debug_2 (in view: work.power_on_seq(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\power_on_seq.v":58:24:58:39|Tristate driver curr_state_debug_3 (in view: work.power_on_seq(verilog)) on net curr_state_debug_3 (in view: work.power_on_seq(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\power_on_seq.v":58:24:58:39|Tristate driver curr_state_debug_4 (in view: work.power_on_seq(verilog)) on net curr_state_debug_4 (in view: work.power_on_seq(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\power_on_seq.v":58:24:58:39|Tristate driver curr_state_debug_5 (in view: work.power_on_seq(verilog)) on net curr_state_debug_5 (in view: work.power_on_seq(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\power_on_seq.v":58:24:58:39|Tristate driver curr_state_debug_6 (in view: work.power_on_seq(verilog)) on net curr_state_debug_6 (in view: work.power_on_seq(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\power_on_seq.v":58:24:58:39|Tristate driver curr_state_debug_7 (in view: work.power_on_seq(verilog)) on net curr_state_debug_7 (in view: work.power_on_seq(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\power_on_seq.v":58:24:58:39|Tristate driver curr_state_debug_8 (in view: work.power_on_seq(verilog)) on net curr_state_debug_8 (in view: work.power_on_seq(verilog)) has its enable tied to GND.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\com_exp_ctrl.v":495:1:495:6|Removing sequential instance o_them_sd_ind (in view: work.com_exp_ctrl(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":106:6:106:11|Removing sequential instance loop\[4\]\.int_trig_level[4] (in view: work.cfg_int_gen_6(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":106:6:106:11|Removing sequential instance loop\[3\]\.int_trig_level[3] (in view: work.cfg_int_gen_6(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":106:6:106:11|Removing sequential instance loop\[1\]\.int_trig_level[1] (in view: work.cfg_int_gen_6(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":106:6:106:11|Removing sequential instance loop\[2\]\.int_trig_level[2] (in view: work.cfg_int_gen_6(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":106:6:106:11|Removing sequential instance loop\[5\]\.int_trig_level[5] (in view: work.cfg_int_gen_6(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":106:6:106:11|Removing sequential instance loop\[0\]\.int_trig_level[0] (in view: work.cfg_int_gen_6(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":106:6:106:11|Removing sequential instance loop\[2\]\.int_trig_level[2] (in view: work.cfg_int_gen_4(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":106:6:106:11|Removing sequential instance loop\[0\]\.int_trig_level[0] (in view: work.cfg_int_gen_4(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":106:6:106:11|Removing sequential instance loop\[3\]\.int_trig_level[3] (in view: work.cfg_int_gen_4(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":106:6:106:11|Removing sequential instance loop\[1\]\.int_trig_level[1] (in view: work.cfg_int_gen_4(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":76:6:76:11|Removing sequential instance loop\[2\]\.int_trig_pos[2] (in view: work.cfg_int_gen_6(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":76:6:76:11|Removing sequential instance loop\[3\]\.int_trig_pos[3] (in view: work.cfg_int_gen_6(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":76:6:76:11|Removing sequential instance loop\[0\]\.int_trig_pos[0] (in view: work.cfg_int_gen_6(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":76:6:76:11|Removing sequential instance loop\[5\]\.int_trig_pos[5] (in view: work.cfg_int_gen_6(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":76:6:76:11|Removing sequential instance loop\[1\]\.int_trig_pos[1] (in view: work.cfg_int_gen_6(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":76:6:76:11|Removing sequential instance loop\[4\]\.int_trig_pos[4] (in view: work.cfg_int_gen_6(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":76:6:76:11|Removing sequential instance loop\[0\]\.int_trig_pos[0] (in view: work.cfg_int_gen_4(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":76:6:76:11|Removing sequential instance loop\[1\]\.int_trig_pos[1] (in view: work.cfg_int_gen_4(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":76:6:76:11|Removing sequential instance loop\[3\]\.int_trig_pos[3] (in view: work.cfg_int_gen_4(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":76:6:76:11|Removing sequential instance loop\[2\]\.int_trig_pos[2] (in view: work.cfg_int_gen_4(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":61:6:61:11|Removing sequential instance loop\[2\]\.int_status_pos[2] (in view: work.cfg_int_gen_6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":61:6:61:11|Removing sequential instance loop\[3\]\.int_status_pos[3] (in view: work.cfg_int_gen_6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":61:6:61:11|Removing sequential instance loop\[0\]\.int_status_pos[0] (in view: work.cfg_int_gen_6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":61:6:61:11|Removing sequential instance loop\[5\]\.int_status_pos[5] (in view: work.cfg_int_gen_6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":61:6:61:11|Removing sequential instance loop\[1\]\.int_status_pos[1] (in view: work.cfg_int_gen_6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":61:6:61:11|Removing sequential instance loop\[4\]\.int_status_pos[4] (in view: work.cfg_int_gen_6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":61:6:61:11|Removing sequential instance loop\[0\]\.int_status_pos[0] (in view: work.cfg_int_gen_4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":61:6:61:11|Removing sequential instance loop\[1\]\.int_status_pos[1] (in view: work.cfg_int_gen_4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":61:6:61:11|Removing sequential instance loop\[3\]\.int_status_pos[3] (in view: work.cfg_int_gen_4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\cfg_int_gen.v":61:6:61:11|Removing sequential instance loop\[2\]\.int_status_pos[2] (in view: work.cfg_int_gen_4(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
Encoding state machine cs[7:0] (in view: work.i2c_slave_50_1_2_4_8_16_32_64_128(verilog))
original code -> new code
00000001 -> 00000001
00000010 -> 00000010
00000100 -> 00000100
00001000 -> 00001000
00010000 -> 00010000
00100000 -> 00100000
01000000 -> 01000000
10000000 -> 10000000
Encoding state machine cur_state[5:0] (in view: work.LPC_IO_CYCLE_Z1(verilog))
original code -> new code
000001 -> 000001
000010 -> 000010
000100 -> 000100
001000 -> 001000
010000 -> 010000
100000 -> 100000
Encoding state machine C_State[8:0] (in view: work.power_on_seq(verilog))
original code -> new code
0000 -> 000000001
0101 -> 000000010
0110 -> 000000100
0111 -> 000001000
1000 -> 000010000
1001 -> 000100000
1010 -> 001000000
1011 -> 010000000
1100 -> 100000000
Encoding state machine current_sta[9:0] (in view: work.com_exp_ctrl(verilog))
original code -> new code
0000000001 -> 0000000001
0000000010 -> 0000000010
0000000100 -> 0000000100
0000001000 -> 0000001000
0000010000 -> 0000010000
0000100000 -> 0000100000
0001000000 -> 0001000000
0010000000 -> 0010000000
0100000000 -> 0100000000
1000000000 -> 1000000000
Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 177MB peak: 177MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
@N: FX1184 |Applying syn_allowed_resources blockrams=8 on top level netlist Belgite_BOARD_CPLD
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
Clock Summary
******************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
------------------------------------------------------------------------------------------------------------------------------
0 - Belgite_BOARD_CPLD|clk_sys_inferred_clock 66.5 MHz 15.038 inferred Inferred_clkgroup_0 917
0 - Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK 100.0 MHz 10.000 inferred Inferred_clkgroup_1 53
==============================================================================================================================
Clock Load Summary
***********************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Belgite_BOARD_CPLD|clk_sys_inferred_clock 917 OSCH_inst.OSC(OSCH) psu_1_pwok1.C - -
Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK 53 COME_CPLD_LPC_CLK(port) LPC_IO_Cycle_Inst.lad_i_r[3:0].C - un1_COME_CPLD_LPC_CLK.I[0](inv)
==========================================================================================================================================================================
@W: MT529 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\i2c_slave.v":279:0:279:5|Found inferred clock Belgite_BOARD_CPLD|clk_sys_inferred_clock which controls 917 sequential elements including i2c_slave_inst0.cs[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
@W: MT529 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\lpc_io_cycle.v":134:4:134:9|Found inferred clock Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK which controls 53 sequential elements including LPC_IO_Cycle_Inst.cur_state[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
@S |Clock Optimization Summary
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
2 non-gated/non-generated clock tree(s) driving 970 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
==================================== Non-Gated/Non-Generated Clocks ====================================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
--------------------------------------------------------------------------------------------------------
@KP:ckid0_0 OSCH_inst.OSC OSCH 917 cnt_300s[8:0]
@KP:ckid0_1 COME_CPLD_LPC_CLK port 53 LPC_IO_Cycle_Inst.cur_state[5]
========================================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 179MB)
Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 180MB peak: 180MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 96MB peak: 180MB)
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Mon Dec 6 18:57:12 2021
###########################################################]
# Mon Dec 6 18:57:13 2021
Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03L-SP1
Install: E:\lattice 3.12\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: HP-PC
Implementation : impl1
Synopsys Lattice Technology Mapper, Version map202003lat, Build 172R, Built Nov 2 2020 09:31:45, @
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 128MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 128MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 132MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB)
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1731:25:1731:28|Tristate driver o_r_sata_pcie_sel (in view: work.Belgite_BOARD_CPLD(verilog)) on net o_r_sata_pcie_sel (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":166:24:166:36|Tristate driver R_TPM_LPCPD_L (in view: work.Belgite_BOARD_CPLD(verilog)) on net R_TPM_LPCPD_L (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1731:25:1731:28|Tristate driver COME_WAKE_N (in view: work.Belgite_BOARD_CPLD(verilog)) on net COME_WAKE_N (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1731:25:1731:28|Tristate driver CB_THRM_N (in view: work.Belgite_BOARD_CPLD(verilog)) on net CB_THRM_N (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1731:25:1731:28|Tristate driver PEWAKE1_N (in view: work.Belgite_BOARD_CPLD(verilog)) on net PEWAKE1_N (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1731:25:1731:28|Tristate driver UCD_LATE_CNTRL_C (in view: work.Belgite_BOARD_CPLD(verilog)) on net UCD_LATE_CNTRL_C (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
@N: MO111 :|Tristate driver led2_t (in view: work.Belgite_BOARD_CPLD(verilog)) on net led2 (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
Available hyper_sources - for debug and ip models
None Found
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 175MB peak: 175MB)
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":910:1:910:6|Removing instance come_bios_dis_reg[3] because it is equivalent to instance come_bios_dis_reg[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":2255:1:2255:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance cnt_300s[8:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1175:1:1175:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance watch_dog_rst_cnt[8:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1321:1:1321:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance cb_rst_dly[5:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1302:1:1302:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance cb_rstp_dly[3:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1083:1:1083:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance cb_rst_l_cnt[5:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":2650:1:2650:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance led_cnt[7:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":681:4:681:9|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance PWR_GD_EARLY_CNT[7:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":699:4:699:9|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance B50282_RST_CNT[6:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":338:1:338:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance internal_por_cnt[4:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":2094:1:2094:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance clk_200ms_count_fan3[7:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":2010:1:2010:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance clk_200ms_count_fan2[7:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1928:1:1928:6|Found counter in view:work.Belgite_BOARD_CPLD(verilog) instance clk_200ms_count_fan1[7:0]
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":910:1:910:6|Removing sequential instance come_bios_dis_reg[2] (in view: work.Belgite_BOARD_CPLD(verilog)) because it does not drive other instances.
@A: BN291 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":910:1:910:6|Boundary register come_bios_dis_reg[2] (in view: work.Belgite_BOARD_CPLD(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1357:1:1357:6|Removing instance reset_source_reg[4] because it is equivalent to instance reset_source_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1357:1:1357:6|Removing instance reset_source_reg[7] because it is equivalent to instance reset_source_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1357:1:1357:6|Removing instance reset_source_reg[5] because it is equivalent to instance reset_source_reg[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":1357:1:1357:6|Removing instance reset_source_reg[6] because it is equivalent to instance reset_source_reg[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\lpc_io_cycle.v":201:4:201:9|Removing sequential instance data_addr[15] (in view: work.LPC_IO_CYCLE_Z1(verilog)) because it does not drive other instances.
@A: BN291 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\lpc_io_cycle.v":201:4:201:9|Boundary register data_addr[15] (in view: work.LPC_IO_CYCLE_Z1(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\lpc_io_cycle.v":201:4:201:9|Removing sequential instance data_addr[14] (in view: work.LPC_IO_CYCLE_Z1(verilog)) because it does not drive other instances.
@A: BN291 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\lpc_io_cycle.v":201:4:201:9|Boundary register data_addr[14] (in view: work.LPC_IO_CYCLE_Z1(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\lpc_io_cycle.v":201:4:201:9|Removing sequential instance data_addr[13] (in view: work.LPC_IO_CYCLE_Z1(verilog)) because it does not drive other instances.
@A: BN291 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\lpc_io_cycle.v":201:4:201:9|Boundary register data_addr[13] (in view: work.LPC_IO_CYCLE_Z1(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\lpc_io_cycle.v":201:4:201:9|Removing sequential instance data_addr[12] (in view: work.LPC_IO_CYCLE_Z1(verilog)) because it does not drive other instances.
@A: BN291 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\lpc_io_cycle.v":201:4:201:9|Boundary register data_addr[12] (in view: work.LPC_IO_CYCLE_Z1(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\lpc_io_cycle.v":100:4:100:9|Found counter in view:work.LPC_IO_CYCLE_Z1(verilog) instance data_write_count[3:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\lpc_io_cycle.v":83:4:83:9|Found counter in view:work.LPC_IO_CYCLE_Z1(verilog) instance data_read_count[3:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\power_on_seq.v":438:1:438:6|Found counter in view:work.power_on_seq(verilog) instance open_sw_power_cnt[7:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\power_on_seq.v":345:1:345:6|Found counter in view:work.power_on_seq(verilog) instance powr_off_sta_cnt[3:0]
@N: FX493 |Applying initial value "0" on instance delay_cnt_1v8_1v2_0v8[0].
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@N: FX493 |Applying initial value "0" on instance delay_cnt_1v8_1v2_0v8[1].
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\com_exp_ctrl.v":553:4:553:9|Found counter in view:work.com_exp_ctrl(verilog) instance boot_cnt[9:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\com_exp_ctrl.v":341:1:341:6|Found counter in view:work.com_exp_ctrl(verilog) instance pwrbtn_tri_dly[4:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\com_exp_ctrl.v":530:4:530:9|Found counter in view:work.com_exp_ctrl(verilog) instance pwr_force_count[3:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\com_exp_ctrl.v":507:4:507:9|Found counter in view:work.com_exp_ctrl(verilog) instance pwr_on_std_count[3:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\com_exp_ctrl.v":361:4:361:9|Found counter in view:work.com_exp_ctrl(verilog) instance wait_s0_cnt[3:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\com_exp_ctrl.v":289:4:289:9|Found counter in view:work.com_exp_ctrl(verilog) instance back_up_cnt[4:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\wd_ctrl.v":127:1:127:6|Found counter in view:work.Wd_Ctrl(verilog) instance s_loss_count[7:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\fan_ctrl.v":85:0:85:5|Found counter in view:work.fan_ctrl_2(verilog) instance fan1_sense_counter[7:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\fan_ctrl.v":51:0:51:5|Found counter in view:work.fan_ctrl_2(verilog) instance counterPWM1[7:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\fan_ctrl.v":85:0:85:5|Found counter in view:work.fan_ctrl_1(verilog) instance fan1_sense_counter[7:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\fan_ctrl.v":51:0:51:5|Found counter in view:work.fan_ctrl_1(verilog) instance counterPWM1[7:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\fan_ctrl.v":85:0:85:5|Found counter in view:work.fan_ctrl_0(verilog) instance fan1_sense_counter[7:0]
@N: MO231 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\fan_ctrl.v":51:0:51:5|Found counter in view:work.fan_ctrl_0(verilog) instance counterPWM1[7:0]
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 184MB peak: 184MB)
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\com_exp_ctrl.v":83:1:83:6|Removing instance com_exp_ctrl_inst1.s_com_sus_sta[0] because it is equivalent to instance cb_rst_n[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
Finished factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 212MB peak: 212MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 197MB peak: 213MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 201MB peak: 213MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 201MB peak: 213MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 202MB peak: 213MB)
Finished preparing to map (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 202MB peak: 213MB)
Finished technology mapping (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 274MB peak: 274MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:10s 0.99ns 1728 / 959
2 0h:00m:10s 0.99ns 1683 / 959
3 0h:00m:10s 0.99ns 1683 / 959
4 0h:00m:11s 0.99ns 1683 / 959
5 0h:00m:11s 0.99ns 1683 / 959
6 0h:00m:11s 0.99ns 1683 / 959
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 275MB peak: 275MB)
@N: BN362 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\com_exp_ctrl.v":591:4:591:9|Removing sequential instance com_exp_ctrl_inst1.o_bios_dis_n[0] (in view: work.Belgite_BOARD_CPLD(verilog)) because it does not drive other instances.
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":19:21:19:24|Tristate driver led2_obuft.un1[0] (in view: work.Belgite_BOARD_CPLD(verilog)) on net led2 (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":21:21:21:36|Tristate driver UCD_LATE_CNTRL_C_obuft.un1[0] (in view: work.Belgite_BOARD_CPLD(verilog)) on net UCD_LATE_CNTRL_C (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
@N: MO111 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_bb\source\belgite_board_cpld.v":57:22:57:30|Tristate driver PEWAKE1_N_obuft.un1[0] (in view: work.Belgite_BOARD_CPLD(verilog)) on net PEWAKE1_N (in view: work.Belgite_BOARD_CPLD(verilog)) has its enable tied to GND.
Finished restoring hierarchy (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:13s; Memory used current: 275MB peak: 275MB)
Start Writing Netlists (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 234MB peak: 275MB)
Writing Analyst data base E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\impl1\synwork\M0_CPLD_V25_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 274MB peak: 275MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: E:\work\CPLD_Program\M0\DVT_pro\M0_CPLD_V25_bb\impl1\M0_CPLD_V25_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 280MB peak: 280MB)
Start final timing analysis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 274MB peak: 280MB)
@W: MT420 |Found inferred clock Belgite_BOARD_CPLD|clk_sys_inferred_clock with period 15.04ns. Please declare a user-defined clock on net clk_sys.
@W: MT420 |Found inferred clock Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK with period 10.00ns. Please declare a user-defined clock on port COME_CPLD_LPC_CLK.
##### START OF TIMING REPORT #####[
# Timing report written on Mon Dec 6 18:57:28 2021
#
Top view: Belgite_BOARD_CPLD
Requested Frequency: 66.5 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
Performance Summary
*******************
Worst slack in design: 1.031
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------------------------------
Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK 100.0 MHz 126.0 MHz 10.000 7.939 1.031 inferred Inferred_clkgroup_1
Belgite_BOARD_CPLD|clk_sys_inferred_clock 66.5 MHz 97.1 MHz 15.037 10.295 4.742 inferred Inferred_clkgroup_0
================================================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Belgite_BOARD_CPLD|clk_sys_inferred_clock Belgite_BOARD_CPLD|clk_sys_inferred_clock | 15.038 4.742 | No paths - | No paths - | No paths -
Belgite_BOARD_CPLD|clk_sys_inferred_clock Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK | Diff grp - | No paths - | No paths - | No paths -
Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK Belgite_BOARD_CPLD|clk_sys_inferred_clock | Diff grp - | No paths - | No paths - | Diff grp -
Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK | 10.000 4.994 | 10.000 4.297 | 5.000 2.067 | 5.000 1.031
============================================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------------------------------------
LPC_IO_Cycle_Inst.cur_state[4] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1S3DX Q cur_state[4] 1.232 1.031
LPC_IO_Cycle_Inst.data_write_count[1] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1P3DX Q data_write_count[1] 1.220 1.075
LPC_IO_Cycle_Inst.data_write_count[2] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1P3DX Q data_write_count[2] 1.220 1.075
LPC_IO_Cycle_Inst.data_write_count[3] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1P3DX Q data_write_count[3] 1.204 1.091
LPC_IO_Cycle_Inst.data_write_count[0] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1P3DX Q data_write_count[0] 1.268 1.099
LPC_IO_Cycle_Inst.cur_state[0] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1S3BX Q cur_state[0] 1.236 2.011
LPC_IO_Cycle_Inst.cur_state[1] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1S3DX Q cur_state[1] 1.236 2.011
LPC_IO_Cycle_Inst.data_read_count[1] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1P3DX Q data_read_count[1] 1.252 2.067
LPC_IO_Cycle_Inst.data_read_count[0] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1P3DX Q data_read_count[0] 1.244 2.075
LPC_IO_Cycle_Inst.data_read_count[2] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1P3DX Q data_read_count[2] 1.228 2.091
================================================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------------------------------------------------------------------
LPC_IO_Cycle_Inst.lad_o[0] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1S3DX D lad_o_6[0] 5.089 1.031
LPC_IO_Cycle_Inst.lad_o[1] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1S3DX D N_1511_i 5.089 1.031
LPC_IO_Cycle_Inst.lad_o[2] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1S3DX D N_1508_i 5.089 1.031
LPC_IO_Cycle_Inst.lad_o[3] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1S3DX D lad_o_6[3] 5.089 1.031
LPC_IO_Cycle_Inst.data_read_count[2] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1P3DX D N_1518_i 5.089 2.011
LPC_IO_Cycle_Inst.cur_state[0] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1S3BX D cur_state_ns_0_i_a2_i[0] 5.089 2.067
LPC_IO_Cycle_Inst.cur_state[4] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1S3DX D cur_state_ns[4] 5.089 2.067
LPC_IO_Cycle_Inst.data_read_count[0] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1P3DX SP N_3078_i 4.528 2.100
LPC_IO_Cycle_Inst.data_read_count[1] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1P3DX SP N_3078_i 4.528 2.100
LPC_IO_Cycle_Inst.data_read_count[2] Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK FD1P3DX SP N_3078_i 4.528 2.100
=====================================================================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 5.000
- Setup time: -0.089
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 5.089
- Propagation time: 4.058
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 1.031
Number of logic level(s): 3
Starting point: LPC_IO_Cycle_Inst.cur_state[4] / Q
Ending point: LPC_IO_Cycle_Inst.lad_o[0] / D
The start point is clocked by Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK [falling] (rise=0.000 fall=5.000 period=10.000) on pin CK
The end point is clocked by Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK [rising] (rise=0.000 fall=5.000 period=10.000) on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------
LPC_IO_Cycle_Inst.cur_state[4] FD1S3DX Q Out 1.232 1.232 r -
cur_state[4] Net - - - - 10
LPC_IO_Cycle_Inst.lad_o_6_0_iv_0_a2[3] ORCALUT4 A In 0.000 1.232 r -
LPC_IO_Cycle_Inst.lad_o_6_0_iv_0_a2[3] ORCALUT4 Z Out 1.193 2.425 r -
N_3978 Net - - - - 4
LPC_IO_Cycle_Inst.lad_o_6_0_iv_0_a3[0] ORCALUT4 C In 0.000 2.425 r -
LPC_IO_Cycle_Inst.lad_o_6_0_iv_0_a3[0] ORCALUT4 Z Out 1.017 3.441 r -
N_3152 Net - - - - 1
LPC_IO_Cycle_Inst.lad_o_6_0_iv_0[0] ORCALUT4 C In 0.000 3.441 r -
LPC_IO_Cycle_Inst.lad_o_6_0_iv_0[0] ORCALUT4 Z Out 0.617 4.058 r -
lad_o_6[0] Net - - - - 1
LPC_IO_Cycle_Inst.lad_o[0] FD1S3DX D In 0.000 4.058 r -
=========================================================================================================
====================================
Detailed Report for Clock: Belgite_BOARD_CPLD|clk_sys_inferred_clock
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------------------------------------------------------
i2c_slave_inst0.o_ram_addr[2] Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1P3DX Q s_i2c_addr[2] 1.272 4.742
i2c_slave_inst0.o_ram_addr[7] Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1P3DX Q s_i2c_addr[7] 1.260 4.754
s_i2c_wr_dly[0] Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1S3DX Q s_i2c_wr_dly[0] 1.188 4.826
s_i2c_wr_dly[1] Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1S3DX Q s_i2c_wr_dly[1] 1.180 4.834
i2c_slave_inst0.o_ram_addr[5] Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1P3DX Q s_i2c_addr[5] 1.392 5.903
s_lpc_wr_dly[0] Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1S3DX Q s_lpc_wr_dly[0] 1.188 5.931
s_lpc_wr_dly[1] Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1S3DX Q s_lpc_wr_dly[1] 1.180 5.939
thm_ctrl_en Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1P3DX Q thm_ctrl_en 1.148 6.010
sw_power_on_reg Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1P3BX Q sw_power_on_reg 1.108 6.050
lm75_int4_thm Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1S3BX Q lm75_int4_thm 1.044 6.114
=========================================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------------------------------------------------------
clk_200ms_count_fan1[7] Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1P3DX D clk_200ms_count_fan1_s[7] 14.932 4.742
clk_200ms_count_fan2[7] Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1P3DX D clk_200ms_count_fan2_s[7] 14.932 4.742
clk_200ms_count_fan3[7] Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1P3DX D clk_200ms_count_fan3_s[7] 14.932 4.742
clk_200ms_count_fan1[5] Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1P3DX D clk_200ms_count_fan1_s[5] 14.932 4.885
clk_200ms_count_fan1[6] Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1P3DX D clk_200ms_count_fan1_s[6] 14.932 4.885
clk_200ms_count_fan2[5] Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1P3DX D clk_200ms_count_fan2_s[5] 14.932 4.885
clk_200ms_count_fan2[6] Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1P3DX D clk_200ms_count_fan2_s[6] 14.932 4.885
clk_200ms_count_fan3[5] Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1P3DX D clk_200ms_count_fan3_s[5] 14.932 4.885
clk_200ms_count_fan3[6] Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1P3DX D clk_200ms_count_fan3_s[6] 14.932 4.885
clk_200ms_count_fan1[3] Belgite_BOARD_CPLD|clk_sys_inferred_clock FD1P3DX D clk_200ms_count_fan1_s[3] 14.932 5.028
==============================================================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 15.037
- Setup time: 0.106
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 14.932
- Propagation time: 10.190
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : 4.742
Number of logic level(s): 10
Starting point: i2c_slave_inst0.o_ram_addr[2] / Q
Ending point: clk_200ms_count_fan1[7] / D
The start point is clocked by Belgite_BOARD_CPLD|clk_sys_inferred_clock [rising] (rise=0.000 fall=7.519 period=15.037) on pin CK
The end point is clocked by Belgite_BOARD_CPLD|clk_sys_inferred_clock [rising] (rise=0.000 fall=7.519 period=15.037) on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------------------------------------
i2c_slave_inst0.o_ram_addr[2] FD1P3DX Q Out 1.272 1.272 r -
s_i2c_addr[2] Net - - - - 18
LPC_IO_Cycle_Inst.un1_cb_rst_n_mask5_0_0_o2_1 ORCALUT4 A In 0.000 1.272 r -
LPC_IO_Cycle_Inst.un1_cb_rst_n_mask5_0_0_o2_1 ORCALUT4 Z Out 1.281 2.553 r -
N_1913 Net - - - - 11
u_watchdog.un1_wd_set_timer_m8_0_0_0_o2_1 ORCALUT4 A In 0.000 2.553 r -
u_watchdog.un1_wd_set_timer_m8_0_0_0_o2_1 ORCALUT4 Z Out 1.193 3.745 r -
N_4179 Net - - - - 4
LPC_IO_Cycle_Inst.un1_USB_EN_OUT7_0_0_o2_0 ORCALUT4 B In 0.000 3.745 r -
LPC_IO_Cycle_Inst.un1_USB_EN_OUT7_0_0_o2_0 ORCALUT4 Z Out 1.225 4.970 r -
N_2178 Net - - - - 5
LPC_IO_Cycle_Inst.un1_USB_EN_OUT7_0_0_o2_0_RNIKLBQ_0 ORCALUT4 B In 0.000 4.970 r -
LPC_IO_Cycle_Inst.un1_USB_EN_OUT7_0_0_o2_0_RNIKLBQ_0 ORCALUT4 Z Out 1.249 6.219 f -
N_1838 Net - - - - 7
LPC_IO_Cycle_Inst.un1_USB_EN_OUT7_0_0_o2_0_RNIM04F3 ORCALUT4 B In 0.000 6.219 f -
LPC_IO_Cycle_Inst.un1_USB_EN_OUT7_0_0_o2_0_RNIM04F3 ORCALUT4 Z Out 0.449 6.668 r -
N_2486_i Net - - - - 9
clk_200ms_count_fan1_cry_0[0] CCU2D A1 In 0.000 6.668 r -
clk_200ms_count_fan1_cry_0[0] CCU2D COUT Out 1.544 8.212 r -
clk_200ms_count_fan1_cry[0] Net - - - - 1
clk_200ms_count_fan1_cry_0[1] CCU2D CIN In 0.000 8.212 r -
clk_200ms_count_fan1_cry_0[1] CCU2D COUT Out 0.143 8.355 r -
clk_200ms_count_fan1_cry[2] Net - - - - 1
clk_200ms_count_fan1_cry_0[3] CCU2D CIN In 0.000 8.355 r -
clk_200ms_count_fan1_cry_0[3] CCU2D COUT Out 0.143 8.498 r -
clk_200ms_count_fan1_cry[4] Net - - - - 1
clk_200ms_count_fan1_cry_0[5] CCU2D CIN In 0.000 8.498 r -
clk_200ms_count_fan1_cry_0[5] CCU2D COUT Out 0.143 8.641 r -
clk_200ms_count_fan1_cry[6] Net - - - - 1
clk_200ms_count_fan1_s_0[7] CCU2D CIN In 0.000 8.641 r -
clk_200ms_count_fan1_s_0[7] CCU2D S0 Out 1.549 10.190 r -
clk_200ms_count_fan1_s[7] Net - - - - 1
clk_200ms_count_fan1[7] FD1P3DX D In 0.000 10.190 r -
========================================================================================================================
##### END OF TIMING REPORT #####]
Timing exceptions that could not be applied
Finished final timing analysis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 275MB peak: 280MB)
Finished timing report (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 275MB peak: 280MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_2000hc-4
Register bits: 958 of 2112 (45%)
PIC Latch: 0
I/O cells: 148
Details:
BB: 5
CCU2D: 171
FD1P3AX: 5
FD1P3BX: 129
FD1P3DX: 483
FD1S3AX: 1
FD1S3BX: 72
FD1S3DX: 238
GSR: 1
IB: 76
IFS1P3BX: 12
IFS1P3DX: 13
INV: 11
L6MUX21: 44
OB: 58
OBZ: 9
OFS1P3BX: 1
OFS1P3DX: 4
ORCALUT4: 1666
OSCH: 1
PFUMX: 172
PUR: 1
VHI: 12
VLO: 12
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:16s; Memory used current: 77MB peak: 280MB)
Process took 0h:00m:16s realtime, 0h:00m:16s cputime
# Mon Dec 6 18:57:29 2021
###########################################################]