| Project Settings |
|---|
| Project Name | proj_1 | Device Name | impl1: Lattice MachXO2 : LCMXO2_2000HC |
| Implementation Name | impl1 | Top Module | Belgite_BOARD_CPLD |
| Pipelining | 1 | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 1000 |
| Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
| Clock Conversion | 1 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
116 |
81 |
0 |
- |
00m:09s |
- |
2021/12/8
15:53:07 |
| (premap) | Complete |
52 |
8 |
0 |
0m:03s |
0m:03s |
180MB |
2021/12/8
15:53:13 |
| (fpga_mapper) | Complete |
55 |
9 |
0 |
0m:23s |
0m:25s |
271MB |
2021/12/8
15:53:39 |
| Multi-srs Generator |
Complete | | | | 00m:01s | | | 2021/12/8
15:53:09 |
| Area Summary |
|---|
|
| Register bits | 958 |
I/O cells | 148 |
| Block RAMs
(v_ram) | 0 |
DSPs
(dsp_used) | 0 |
| ORCA LUTs
(total_luts) | 1683 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK | 100.0 MHz | 124.1 MHz | 0.971 |
| Belgite_BOARD_CPLD|clk_sys_inferred_clock | 66.5 MHz | 98.8 MHz | 4.913 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 2 / 0 |
| |
|