@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_aa\source\power_on_seq.v":400:1:400:6|Removing sequential instance u_power_seq.pwr_en_3v3_mdio because it is equivalent to instance u_power_seq.pwr_en_1v8. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_aa\source\power_on_seq.v":400:1:400:6|Removing sequential instance u_power_seq.pwr_en_1v8 because it is equivalent to instance u_power_seq.pwr_en_1v2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_aa\source\power_on_seq.v":400:1:400:6|Removing sequential instance u_power_seq.pwr_en_1v2 because it is equivalent to instance u_power_seq.pwr_en_0v8. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_aa\source\power_on_seq.v":386:1:386:6|Removing sequential instance u_power_seq.pwr_en_0v8_avs because it is equivalent to instance u_power_seq.pwr_en_1v0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_aa\source\com_exp_ctrl.v":621:4:621:9|Removing sequential instance com_exp_ctrl_inst1.o_com_5v_enable because it is equivalent to instance com_exp_ctrl_inst1.o_com_12v_enable. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MT529 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_aa\source\i2c_slave.v":279:0:279:5|Found inferred clock Belgite_BOARD_CPLD|clk_sys_inferred_clock which controls 917 sequential elements including i2c_slave_inst0.cs[7]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
@W: MT529 :"e:\work\cpld_program\m0\dvt_pro\m0_cpld_v25_aa\source\lpc_io_cycle.v":134:4:134:9|Found inferred clock Belgite_BOARD_CPLD|COME_CPLD_LPC_CLK which controls 53 sequential elements including LPC_IO_Cycle_Inst.cur_state[5]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
