Place & Route TRACE Report
Loading design for application trce from file m0_cpld_v25_impl1.ncd.
Design name: Belgite_BOARD_CPLD
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-2000HC
Package: FTBGA256
Performance: 4
Loading device for application trce from file 'xo2c2000.nph' in environment: E:/lattice 3.12/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Wed Dec 08 15:55:03 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o M0_CPLD_V25_impl1.twr -gui -msgset E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_aa/promote.xml M0_CPLD_V25_impl1.ncd M0_CPLD_V25_impl1.prf
Design file: m0_cpld_v25_impl1.ncd
Preference file: m0_cpld_v25_impl1.prf
Device,speed: LCMXO2-2000HC,4
Report level: verbose report, limited to 10 items per preference
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Preference Summary
FREQUENCY NET "clk_sys" 66.500000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
Report: 75.381MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY NET "clk_sys" 66.500000 MHz ;
4096 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 1.772ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_i2c_wr_dly[0] (from clk_sys +)
Destination: FF Data in cnt_300s[8] (to clk_sys +)
Delay: 13.100ns (42.5% logic, 57.5% route), 12 logic levels.
Constraint Details:
13.100ns physical path delay SLICE_524 to SLICE_122 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 1.772ns
Physical Path Details:
Data path SLICE_524 to SLICE_122:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C9D.CLK to R7C9D.Q0 SLICE_524 (from clk_sys)
ROUTE 5 1.759 R7C9D.Q0 to R9C12B.C0 s_i2c_wr_dly[0]
CTOF_DEL --- 0.495 R9C12B.C0 to R9C12B.F0 SLICE_931
ROUTE 4 0.975 R9C12B.F0 to R10C13D.D1 s_i2c_wr_en
CTOF_DEL --- 0.495 R10C13D.D1 to R10C13D.F1 LPC_IO_Cycle_Inst/SLICE_984
ROUTE 3 0.662 R10C13D.F1 to R10C14A.D1 LPC_IO_Cycle_Inst/N_879
CTOF_DEL --- 0.495 R10C14A.D1 to R10C14A.F1 LPC_IO_Cycle_Inst/SLICE_988
ROUTE 2 0.445 R10C14A.F1 to R10C14B.C0 LPC_IO_Cycle_Inst/N_1605_1
CTOF_DEL --- 0.495 R10C14B.C0 to R10C14B.F0 LPC_IO_Cycle_Inst/SLICE_993
ROUTE 2 0.967 R10C14B.F0 to R9C13C.D0 LPC_IO_Cycle_Inst/N_3102
CTOF_DEL --- 0.495 R9C13C.D0 to R9C13C.F0 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 2 0.445 R9C13C.F0 to R9C13C.C1 LPC_IO_Cycle_Inst/cnt_300s_1_sqmuxa_i_0_o2_2
CTOF_DEL --- 0.495 R9C13C.C1 to R9C13C.F1 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 10 2.273 R9C13C.F1 to R9C5A.B0 cnt_300s
C0TOFCO_DE --- 1.023 R9C5A.B0 to R9C5A.FCO SLICE_126
ROUTE 1 0.000 R9C5A.FCO to R9C5B.FCI cnt_300s_cry[0]
FCITOFCO_D --- 0.162 R9C5B.FCI to R9C5B.FCO SLICE_125
ROUTE 1 0.000 R9C5B.FCO to R9C5C.FCI cnt_300s_cry[2]
FCITOFCO_D --- 0.162 R9C5C.FCI to R9C5C.FCO SLICE_124
ROUTE 1 0.000 R9C5C.FCO to R9C5D.FCI cnt_300s_cry[4]
FCITOFCO_D --- 0.162 R9C5D.FCI to R9C5D.FCO SLICE_123
ROUTE 1 0.000 R9C5D.FCO to R9C6A.FCI cnt_300s_cry[6]
FCITOF1_DE --- 0.643 R9C6A.FCI to R9C6A.F1 SLICE_122
ROUTE 1 0.000 R9C6A.F1 to R9C6A.DI1 cnt_300s_s[8] (to clk_sys)
--------
13.100 (42.5% logic, 57.5% route), 12 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_524:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R7C9D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_122:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R9C6A.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.830ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_i2c_wr_dly[0] (from clk_sys +)
Destination: FF Data in cnt_300s[7] (to clk_sys +)
Delay: 13.042ns (42.3% logic, 57.7% route), 12 logic levels.
Constraint Details:
13.042ns physical path delay SLICE_524 to SLICE_122 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 1.830ns
Physical Path Details:
Data path SLICE_524 to SLICE_122:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C9D.CLK to R7C9D.Q0 SLICE_524 (from clk_sys)
ROUTE 5 1.759 R7C9D.Q0 to R9C12B.C0 s_i2c_wr_dly[0]
CTOF_DEL --- 0.495 R9C12B.C0 to R9C12B.F0 SLICE_931
ROUTE 4 0.975 R9C12B.F0 to R10C13D.D1 s_i2c_wr_en
CTOF_DEL --- 0.495 R10C13D.D1 to R10C13D.F1 LPC_IO_Cycle_Inst/SLICE_984
ROUTE 3 0.662 R10C13D.F1 to R10C14A.D1 LPC_IO_Cycle_Inst/N_879
CTOF_DEL --- 0.495 R10C14A.D1 to R10C14A.F1 LPC_IO_Cycle_Inst/SLICE_988
ROUTE 2 0.445 R10C14A.F1 to R10C14B.C0 LPC_IO_Cycle_Inst/N_1605_1
CTOF_DEL --- 0.495 R10C14B.C0 to R10C14B.F0 LPC_IO_Cycle_Inst/SLICE_993
ROUTE 2 0.967 R10C14B.F0 to R9C13C.D0 LPC_IO_Cycle_Inst/N_3102
CTOF_DEL --- 0.495 R9C13C.D0 to R9C13C.F0 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 2 0.445 R9C13C.F0 to R9C13C.C1 LPC_IO_Cycle_Inst/cnt_300s_1_sqmuxa_i_0_o2_2
CTOF_DEL --- 0.495 R9C13C.C1 to R9C13C.F1 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 10 2.273 R9C13C.F1 to R9C5A.B0 cnt_300s
C0TOFCO_DE --- 1.023 R9C5A.B0 to R9C5A.FCO SLICE_126
ROUTE 1 0.000 R9C5A.FCO to R9C5B.FCI cnt_300s_cry[0]
FCITOFCO_D --- 0.162 R9C5B.FCI to R9C5B.FCO SLICE_125
ROUTE 1 0.000 R9C5B.FCO to R9C5C.FCI cnt_300s_cry[2]
FCITOFCO_D --- 0.162 R9C5C.FCI to R9C5C.FCO SLICE_124
ROUTE 1 0.000 R9C5C.FCO to R9C5D.FCI cnt_300s_cry[4]
FCITOFCO_D --- 0.162 R9C5D.FCI to R9C5D.FCO SLICE_123
ROUTE 1 0.000 R9C5D.FCO to R9C6A.FCI cnt_300s_cry[6]
FCITOF0_DE --- 0.585 R9C6A.FCI to R9C6A.F0 SLICE_122
ROUTE 1 0.000 R9C6A.F0 to R9C6A.DI0 cnt_300s_s[7] (to clk_sys)
--------
13.042 (42.3% logic, 57.7% route), 12 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_524:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R7C9D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_122:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R9C6A.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.893ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_i2c_wr_dly[0] (from clk_sys +)
Destination: FF Data in cnt_300s[8] (to clk_sys +)
Delay: 12.979ns (41.9% logic, 58.1% route), 12 logic levels.
Constraint Details:
12.979ns physical path delay SLICE_524 to SLICE_122 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 1.893ns
Physical Path Details:
Data path SLICE_524 to SLICE_122:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C9D.CLK to R7C9D.Q0 SLICE_524 (from clk_sys)
ROUTE 5 1.759 R7C9D.Q0 to R9C12B.C0 s_i2c_wr_dly[0]
CTOF_DEL --- 0.495 R9C12B.C0 to R9C12B.F0 SLICE_931
ROUTE 4 0.975 R9C12B.F0 to R10C13D.D1 s_i2c_wr_en
CTOF_DEL --- 0.495 R10C13D.D1 to R10C13D.F1 LPC_IO_Cycle_Inst/SLICE_984
ROUTE 3 0.662 R10C13D.F1 to R10C14A.D1 LPC_IO_Cycle_Inst/N_879
CTOF_DEL --- 0.495 R10C14A.D1 to R10C14A.F1 LPC_IO_Cycle_Inst/SLICE_988
ROUTE 2 0.445 R10C14A.F1 to R10C14B.C0 LPC_IO_Cycle_Inst/N_1605_1
CTOF_DEL --- 0.495 R10C14B.C0 to R10C14B.F0 LPC_IO_Cycle_Inst/SLICE_993
ROUTE 2 0.967 R10C14B.F0 to R9C13C.D0 LPC_IO_Cycle_Inst/N_3102
CTOF_DEL --- 0.495 R9C13C.D0 to R9C13C.F0 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 2 0.445 R9C13C.F0 to R9C13C.C1 LPC_IO_Cycle_Inst/cnt_300s_1_sqmuxa_i_0_o2_2
CTOF_DEL --- 0.495 R9C13C.C1 to R9C13C.F1 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 10 2.286 R9C13C.F1 to R9C5A.A1 cnt_300s
C1TOFCO_DE --- 0.889 R9C5A.A1 to R9C5A.FCO SLICE_126
ROUTE 1 0.000 R9C5A.FCO to R9C5B.FCI cnt_300s_cry[0]
FCITOFCO_D --- 0.162 R9C5B.FCI to R9C5B.FCO SLICE_125
ROUTE 1 0.000 R9C5B.FCO to R9C5C.FCI cnt_300s_cry[2]
FCITOFCO_D --- 0.162 R9C5C.FCI to R9C5C.FCO SLICE_124
ROUTE 1 0.000 R9C5C.FCO to R9C5D.FCI cnt_300s_cry[4]
FCITOFCO_D --- 0.162 R9C5D.FCI to R9C5D.FCO SLICE_123
ROUTE 1 0.000 R9C5D.FCO to R9C6A.FCI cnt_300s_cry[6]
FCITOF1_DE --- 0.643 R9C6A.FCI to R9C6A.F1 SLICE_122
ROUTE 1 0.000 R9C6A.F1 to R9C6A.DI1 cnt_300s_s[8] (to clk_sys)
--------
12.979 (41.9% logic, 58.1% route), 12 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_524:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R7C9D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_122:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R9C6A.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.921ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_i2c_wr_dly[0] (from clk_sys +)
Destination: FF Data in cnt_300s[8] (to clk_sys +)
Delay: 12.951ns (41.8% logic, 58.2% route), 11 logic levels.
Constraint Details:
12.951ns physical path delay SLICE_524 to SLICE_122 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 1.921ns
Physical Path Details:
Data path SLICE_524 to SLICE_122:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C9D.CLK to R7C9D.Q0 SLICE_524 (from clk_sys)
ROUTE 5 1.759 R7C9D.Q0 to R9C12B.C0 s_i2c_wr_dly[0]
CTOF_DEL --- 0.495 R9C12B.C0 to R9C12B.F0 SLICE_931
ROUTE 4 0.975 R9C12B.F0 to R10C13D.D1 s_i2c_wr_en
CTOF_DEL --- 0.495 R10C13D.D1 to R10C13D.F1 LPC_IO_Cycle_Inst/SLICE_984
ROUTE 3 0.662 R10C13D.F1 to R10C14A.D1 LPC_IO_Cycle_Inst/N_879
CTOF_DEL --- 0.495 R10C14A.D1 to R10C14A.F1 LPC_IO_Cycle_Inst/SLICE_988
ROUTE 2 0.445 R10C14A.F1 to R10C14B.C0 LPC_IO_Cycle_Inst/N_1605_1
CTOF_DEL --- 0.495 R10C14B.C0 to R10C14B.F0 LPC_IO_Cycle_Inst/SLICE_993
ROUTE 2 0.967 R10C14B.F0 to R9C13C.D0 LPC_IO_Cycle_Inst/N_3102
CTOF_DEL --- 0.495 R9C13C.D0 to R9C13C.F0 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 2 0.445 R9C13C.F0 to R9C13C.C1 LPC_IO_Cycle_Inst/cnt_300s_1_sqmuxa_i_0_o2_2
CTOF_DEL --- 0.495 R9C13C.C1 to R9C13C.F1 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 10 2.286 R9C13C.F1 to R9C5B.A0 cnt_300s
C0TOFCO_DE --- 1.023 R9C5B.A0 to R9C5B.FCO SLICE_125
ROUTE 1 0.000 R9C5B.FCO to R9C5C.FCI cnt_300s_cry[2]
FCITOFCO_D --- 0.162 R9C5C.FCI to R9C5C.FCO SLICE_124
ROUTE 1 0.000 R9C5C.FCO to R9C5D.FCI cnt_300s_cry[4]
FCITOFCO_D --- 0.162 R9C5D.FCI to R9C5D.FCO SLICE_123
ROUTE 1 0.000 R9C5D.FCO to R9C6A.FCI cnt_300s_cry[6]
FCITOF1_DE --- 0.643 R9C6A.FCI to R9C6A.F1 SLICE_122
ROUTE 1 0.000 R9C6A.F1 to R9C6A.DI1 cnt_300s_s[8] (to clk_sys)
--------
12.951 (41.8% logic, 58.2% route), 11 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_524:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R7C9D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_122:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R9C6A.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.934ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_i2c_wr_dly[0] (from clk_sys +)
Destination: FF Data in cnt_300s[6] (to clk_sys +)
Delay: 12.938ns (41.8% logic, 58.2% route), 11 logic levels.
Constraint Details:
12.938ns physical path delay SLICE_524 to SLICE_123 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 1.934ns
Physical Path Details:
Data path SLICE_524 to SLICE_123:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C9D.CLK to R7C9D.Q0 SLICE_524 (from clk_sys)
ROUTE 5 1.759 R7C9D.Q0 to R9C12B.C0 s_i2c_wr_dly[0]
CTOF_DEL --- 0.495 R9C12B.C0 to R9C12B.F0 SLICE_931
ROUTE 4 0.975 R9C12B.F0 to R10C13D.D1 s_i2c_wr_en
CTOF_DEL --- 0.495 R10C13D.D1 to R10C13D.F1 LPC_IO_Cycle_Inst/SLICE_984
ROUTE 3 0.662 R10C13D.F1 to R10C14A.D1 LPC_IO_Cycle_Inst/N_879
CTOF_DEL --- 0.495 R10C14A.D1 to R10C14A.F1 LPC_IO_Cycle_Inst/SLICE_988
ROUTE 2 0.445 R10C14A.F1 to R10C14B.C0 LPC_IO_Cycle_Inst/N_1605_1
CTOF_DEL --- 0.495 R10C14B.C0 to R10C14B.F0 LPC_IO_Cycle_Inst/SLICE_993
ROUTE 2 0.967 R10C14B.F0 to R9C13C.D0 LPC_IO_Cycle_Inst/N_3102
CTOF_DEL --- 0.495 R9C13C.D0 to R9C13C.F0 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 2 0.445 R9C13C.F0 to R9C13C.C1 LPC_IO_Cycle_Inst/cnt_300s_1_sqmuxa_i_0_o2_2
CTOF_DEL --- 0.495 R9C13C.C1 to R9C13C.F1 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 10 2.273 R9C13C.F1 to R9C5A.B0 cnt_300s
C0TOFCO_DE --- 1.023 R9C5A.B0 to R9C5A.FCO SLICE_126
ROUTE 1 0.000 R9C5A.FCO to R9C5B.FCI cnt_300s_cry[0]
FCITOFCO_D --- 0.162 R9C5B.FCI to R9C5B.FCO SLICE_125
ROUTE 1 0.000 R9C5B.FCO to R9C5C.FCI cnt_300s_cry[2]
FCITOFCO_D --- 0.162 R9C5C.FCI to R9C5C.FCO SLICE_124
ROUTE 1 0.000 R9C5C.FCO to R9C5D.FCI cnt_300s_cry[4]
FCITOF1_DE --- 0.643 R9C5D.FCI to R9C5D.F1 SLICE_123
ROUTE 1 0.000 R9C5D.F1 to R9C5D.DI1 cnt_300s_s[6] (to clk_sys)
--------
12.938 (41.8% logic, 58.2% route), 11 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_524:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R7C9D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_123:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R9C5D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.951ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_i2c_wr_dly[0] (from clk_sys +)
Destination: FF Data in cnt_300s[7] (to clk_sys +)
Delay: 12.921ns (41.7% logic, 58.3% route), 12 logic levels.
Constraint Details:
12.921ns physical path delay SLICE_524 to SLICE_122 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 1.951ns
Physical Path Details:
Data path SLICE_524 to SLICE_122:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C9D.CLK to R7C9D.Q0 SLICE_524 (from clk_sys)
ROUTE 5 1.759 R7C9D.Q0 to R9C12B.C0 s_i2c_wr_dly[0]
CTOF_DEL --- 0.495 R9C12B.C0 to R9C12B.F0 SLICE_931
ROUTE 4 0.975 R9C12B.F0 to R10C13D.D1 s_i2c_wr_en
CTOF_DEL --- 0.495 R10C13D.D1 to R10C13D.F1 LPC_IO_Cycle_Inst/SLICE_984
ROUTE 3 0.662 R10C13D.F1 to R10C14A.D1 LPC_IO_Cycle_Inst/N_879
CTOF_DEL --- 0.495 R10C14A.D1 to R10C14A.F1 LPC_IO_Cycle_Inst/SLICE_988
ROUTE 2 0.445 R10C14A.F1 to R10C14B.C0 LPC_IO_Cycle_Inst/N_1605_1
CTOF_DEL --- 0.495 R10C14B.C0 to R10C14B.F0 LPC_IO_Cycle_Inst/SLICE_993
ROUTE 2 0.967 R10C14B.F0 to R9C13C.D0 LPC_IO_Cycle_Inst/N_3102
CTOF_DEL --- 0.495 R9C13C.D0 to R9C13C.F0 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 2 0.445 R9C13C.F0 to R9C13C.C1 LPC_IO_Cycle_Inst/cnt_300s_1_sqmuxa_i_0_o2_2
CTOF_DEL --- 0.495 R9C13C.C1 to R9C13C.F1 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 10 2.286 R9C13C.F1 to R9C5A.A1 cnt_300s
C1TOFCO_DE --- 0.889 R9C5A.A1 to R9C5A.FCO SLICE_126
ROUTE 1 0.000 R9C5A.FCO to R9C5B.FCI cnt_300s_cry[0]
FCITOFCO_D --- 0.162 R9C5B.FCI to R9C5B.FCO SLICE_125
ROUTE 1 0.000 R9C5B.FCO to R9C5C.FCI cnt_300s_cry[2]
FCITOFCO_D --- 0.162 R9C5C.FCI to R9C5C.FCO SLICE_124
ROUTE 1 0.000 R9C5C.FCO to R9C5D.FCI cnt_300s_cry[4]
FCITOFCO_D --- 0.162 R9C5D.FCI to R9C5D.FCO SLICE_123
ROUTE 1 0.000 R9C5D.FCO to R9C6A.FCI cnt_300s_cry[6]
FCITOF0_DE --- 0.585 R9C6A.FCI to R9C6A.F0 SLICE_122
ROUTE 1 0.000 R9C6A.F0 to R9C6A.DI0 cnt_300s_s[7] (to clk_sys)
--------
12.921 (41.7% logic, 58.3% route), 12 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_524:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R7C9D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_122:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R9C6A.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.979ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_i2c_wr_dly[0] (from clk_sys +)
Destination: FF Data in cnt_300s[7] (to clk_sys +)
Delay: 12.893ns (41.5% logic, 58.5% route), 11 logic levels.
Constraint Details:
12.893ns physical path delay SLICE_524 to SLICE_122 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 1.979ns
Physical Path Details:
Data path SLICE_524 to SLICE_122:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C9D.CLK to R7C9D.Q0 SLICE_524 (from clk_sys)
ROUTE 5 1.759 R7C9D.Q0 to R9C12B.C0 s_i2c_wr_dly[0]
CTOF_DEL --- 0.495 R9C12B.C0 to R9C12B.F0 SLICE_931
ROUTE 4 0.975 R9C12B.F0 to R10C13D.D1 s_i2c_wr_en
CTOF_DEL --- 0.495 R10C13D.D1 to R10C13D.F1 LPC_IO_Cycle_Inst/SLICE_984
ROUTE 3 0.662 R10C13D.F1 to R10C14A.D1 LPC_IO_Cycle_Inst/N_879
CTOF_DEL --- 0.495 R10C14A.D1 to R10C14A.F1 LPC_IO_Cycle_Inst/SLICE_988
ROUTE 2 0.445 R10C14A.F1 to R10C14B.C0 LPC_IO_Cycle_Inst/N_1605_1
CTOF_DEL --- 0.495 R10C14B.C0 to R10C14B.F0 LPC_IO_Cycle_Inst/SLICE_993
ROUTE 2 0.967 R10C14B.F0 to R9C13C.D0 LPC_IO_Cycle_Inst/N_3102
CTOF_DEL --- 0.495 R9C13C.D0 to R9C13C.F0 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 2 0.445 R9C13C.F0 to R9C13C.C1 LPC_IO_Cycle_Inst/cnt_300s_1_sqmuxa_i_0_o2_2
CTOF_DEL --- 0.495 R9C13C.C1 to R9C13C.F1 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 10 2.286 R9C13C.F1 to R9C5B.A0 cnt_300s
C0TOFCO_DE --- 1.023 R9C5B.A0 to R9C5B.FCO SLICE_125
ROUTE 1 0.000 R9C5B.FCO to R9C5C.FCI cnt_300s_cry[2]
FCITOFCO_D --- 0.162 R9C5C.FCI to R9C5C.FCO SLICE_124
ROUTE 1 0.000 R9C5C.FCO to R9C5D.FCI cnt_300s_cry[4]
FCITOFCO_D --- 0.162 R9C5D.FCI to R9C5D.FCO SLICE_123
ROUTE 1 0.000 R9C5D.FCO to R9C6A.FCI cnt_300s_cry[6]
FCITOF0_DE --- 0.585 R9C6A.FCI to R9C6A.F0 SLICE_122
ROUTE 1 0.000 R9C6A.F0 to R9C6A.DI0 cnt_300s_s[7] (to clk_sys)
--------
12.893 (41.5% logic, 58.5% route), 11 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_524:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R7C9D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_122:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R9C6A.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.992ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_i2c_wr_dly[0] (from clk_sys +)
Destination: FF Data in cnt_300s[5] (to clk_sys +)
Delay: 12.880ns (41.6% logic, 58.4% route), 11 logic levels.
Constraint Details:
12.880ns physical path delay SLICE_524 to SLICE_123 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 1.992ns
Physical Path Details:
Data path SLICE_524 to SLICE_123:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C9D.CLK to R7C9D.Q0 SLICE_524 (from clk_sys)
ROUTE 5 1.759 R7C9D.Q0 to R9C12B.C0 s_i2c_wr_dly[0]
CTOF_DEL --- 0.495 R9C12B.C0 to R9C12B.F0 SLICE_931
ROUTE 4 0.975 R9C12B.F0 to R10C13D.D1 s_i2c_wr_en
CTOF_DEL --- 0.495 R10C13D.D1 to R10C13D.F1 LPC_IO_Cycle_Inst/SLICE_984
ROUTE 3 0.662 R10C13D.F1 to R10C14A.D1 LPC_IO_Cycle_Inst/N_879
CTOF_DEL --- 0.495 R10C14A.D1 to R10C14A.F1 LPC_IO_Cycle_Inst/SLICE_988
ROUTE 2 0.445 R10C14A.F1 to R10C14B.C0 LPC_IO_Cycle_Inst/N_1605_1
CTOF_DEL --- 0.495 R10C14B.C0 to R10C14B.F0 LPC_IO_Cycle_Inst/SLICE_993
ROUTE 2 0.967 R10C14B.F0 to R9C13C.D0 LPC_IO_Cycle_Inst/N_3102
CTOF_DEL --- 0.495 R9C13C.D0 to R9C13C.F0 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 2 0.445 R9C13C.F0 to R9C13C.C1 LPC_IO_Cycle_Inst/cnt_300s_1_sqmuxa_i_0_o2_2
CTOF_DEL --- 0.495 R9C13C.C1 to R9C13C.F1 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 10 2.273 R9C13C.F1 to R9C5A.B0 cnt_300s
C0TOFCO_DE --- 1.023 R9C5A.B0 to R9C5A.FCO SLICE_126
ROUTE 1 0.000 R9C5A.FCO to R9C5B.FCI cnt_300s_cry[0]
FCITOFCO_D --- 0.162 R9C5B.FCI to R9C5B.FCO SLICE_125
ROUTE 1 0.000 R9C5B.FCO to R9C5C.FCI cnt_300s_cry[2]
FCITOFCO_D --- 0.162 R9C5C.FCI to R9C5C.FCO SLICE_124
ROUTE 1 0.000 R9C5C.FCO to R9C5D.FCI cnt_300s_cry[4]
FCITOF0_DE --- 0.585 R9C5D.FCI to R9C5D.F0 SLICE_123
ROUTE 1 0.000 R9C5D.F0 to R9C5D.DI0 cnt_300s_s[5] (to clk_sys)
--------
12.880 (41.6% logic, 58.4% route), 11 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_524:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R7C9D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_123:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R9C5D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 2.055ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_i2c_wr_dly[0] (from clk_sys +)
Destination: FF Data in cnt_300s[8] (to clk_sys +)
Delay: 12.817ns (41.2% logic, 58.8% route), 11 logic levels.
Constraint Details:
12.817ns physical path delay SLICE_524 to SLICE_122 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 2.055ns
Physical Path Details:
Data path SLICE_524 to SLICE_122:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C9D.CLK to R7C9D.Q0 SLICE_524 (from clk_sys)
ROUTE 5 1.759 R7C9D.Q0 to R9C12B.C0 s_i2c_wr_dly[0]
CTOF_DEL --- 0.495 R9C12B.C0 to R9C12B.F0 SLICE_931
ROUTE 4 0.975 R9C12B.F0 to R10C13D.D1 s_i2c_wr_en
CTOF_DEL --- 0.495 R10C13D.D1 to R10C13D.F1 LPC_IO_Cycle_Inst/SLICE_984
ROUTE 3 0.662 R10C13D.F1 to R10C14A.D1 LPC_IO_Cycle_Inst/N_879
CTOF_DEL --- 0.495 R10C14A.D1 to R10C14A.F1 LPC_IO_Cycle_Inst/SLICE_988
ROUTE 2 0.445 R10C14A.F1 to R10C14B.C0 LPC_IO_Cycle_Inst/N_1605_1
CTOF_DEL --- 0.495 R10C14B.C0 to R10C14B.F0 LPC_IO_Cycle_Inst/SLICE_993
ROUTE 2 0.967 R10C14B.F0 to R9C13C.D0 LPC_IO_Cycle_Inst/N_3102
CTOF_DEL --- 0.495 R9C13C.D0 to R9C13C.F0 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 2 0.445 R9C13C.F0 to R9C13C.C1 LPC_IO_Cycle_Inst/cnt_300s_1_sqmuxa_i_0_o2_2
CTOF_DEL --- 0.495 R9C13C.C1 to R9C13C.F1 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 10 2.286 R9C13C.F1 to R9C5B.A1 cnt_300s
C1TOFCO_DE --- 0.889 R9C5B.A1 to R9C5B.FCO SLICE_125
ROUTE 1 0.000 R9C5B.FCO to R9C5C.FCI cnt_300s_cry[2]
FCITOFCO_D --- 0.162 R9C5C.FCI to R9C5C.FCO SLICE_124
ROUTE 1 0.000 R9C5C.FCO to R9C5D.FCI cnt_300s_cry[4]
FCITOFCO_D --- 0.162 R9C5D.FCI to R9C5D.FCO SLICE_123
ROUTE 1 0.000 R9C5D.FCO to R9C6A.FCI cnt_300s_cry[6]
FCITOF1_DE --- 0.643 R9C6A.FCI to R9C6A.F1 SLICE_122
ROUTE 1 0.000 R9C6A.F1 to R9C6A.DI1 cnt_300s_s[8] (to clk_sys)
--------
12.817 (41.2% logic, 58.8% route), 11 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_524:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R7C9D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_122:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R9C6A.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 2.055ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_i2c_wr_dly[0] (from clk_sys +)
Destination: FF Data in cnt_300s[6] (to clk_sys +)
Delay: 12.817ns (41.2% logic, 58.8% route), 11 logic levels.
Constraint Details:
12.817ns physical path delay SLICE_524 to SLICE_123 meets
15.038ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 14.872ns) by 2.055ns
Physical Path Details:
Data path SLICE_524 to SLICE_123:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R7C9D.CLK to R7C9D.Q0 SLICE_524 (from clk_sys)
ROUTE 5 1.759 R7C9D.Q0 to R9C12B.C0 s_i2c_wr_dly[0]
CTOF_DEL --- 0.495 R9C12B.C0 to R9C12B.F0 SLICE_931
ROUTE 4 0.975 R9C12B.F0 to R10C13D.D1 s_i2c_wr_en
CTOF_DEL --- 0.495 R10C13D.D1 to R10C13D.F1 LPC_IO_Cycle_Inst/SLICE_984
ROUTE 3 0.662 R10C13D.F1 to R10C14A.D1 LPC_IO_Cycle_Inst/N_879
CTOF_DEL --- 0.495 R10C14A.D1 to R10C14A.F1 LPC_IO_Cycle_Inst/SLICE_988
ROUTE 2 0.445 R10C14A.F1 to R10C14B.C0 LPC_IO_Cycle_Inst/N_1605_1
CTOF_DEL --- 0.495 R10C14B.C0 to R10C14B.F0 LPC_IO_Cycle_Inst/SLICE_993
ROUTE 2 0.967 R10C14B.F0 to R9C13C.D0 LPC_IO_Cycle_Inst/N_3102
CTOF_DEL --- 0.495 R9C13C.D0 to R9C13C.F0 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 2 0.445 R9C13C.F0 to R9C13C.C1 LPC_IO_Cycle_Inst/cnt_300s_1_sqmuxa_i_0_o2_2
CTOF_DEL --- 0.495 R9C13C.C1 to R9C13C.F1 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 10 2.286 R9C13C.F1 to R9C5A.A1 cnt_300s
C1TOFCO_DE --- 0.889 R9C5A.A1 to R9C5A.FCO SLICE_126
ROUTE 1 0.000 R9C5A.FCO to R9C5B.FCI cnt_300s_cry[0]
FCITOFCO_D --- 0.162 R9C5B.FCI to R9C5B.FCO SLICE_125
ROUTE 1 0.000 R9C5B.FCO to R9C5C.FCI cnt_300s_cry[2]
FCITOFCO_D --- 0.162 R9C5C.FCI to R9C5C.FCO SLICE_124
ROUTE 1 0.000 R9C5C.FCO to R9C5D.FCI cnt_300s_cry[4]
FCITOF1_DE --- 0.643 R9C5D.FCI to R9C5D.F1 SLICE_123
ROUTE 1 0.000 R9C5D.F1 to R9C5D.DI1 cnt_300s_s[6] (to clk_sys)
--------
12.817 (41.2% logic, 58.8% route), 11 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_524:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R7C9D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_123:
Name Fanout Delay (ns) Site Resource
ROUTE 553 3.977 OSC.OSC to R9C5D.CLK clk_sys
--------
3.977 (0.0% logic, 100.0% route), 0 logic levels.
Report: 75.381MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_sys" 66.500000 MHz ; | 66.500 MHz| 75.381 MHz| 12
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: clk_sys Source: OSCH_inst.OSC Loads: 553
Covered under: FREQUENCY NET "clk_sys" 66.500000 MHz ;
Data transfers from:
Clock Domain: COME_CPLD_LPC_CLK_c Source: COME_CPLD_LPC_CLK.PAD
Not reported because source and destination domains are unrelated.
Clock Domain: COME_CPLD_LPC_CLK_c Source: COME_CPLD_LPC_CLK.PAD Loads: 29
No transfer within this clock domain is found
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 18134 paths, 1 nets, and 7056 connections (80.13% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
Wed Dec 08 15:55:04 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o M0_CPLD_V25_impl1.twr -gui -msgset E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_aa/promote.xml M0_CPLD_V25_impl1.ncd M0_CPLD_V25_impl1.prf
Design file: m0_cpld_v25_impl1.ncd
Preference file: m0_cpld_v25_impl1.prf
Device,speed: LCMXO2-2000HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "clk_sys" 66.500000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "clk_sys" 66.500000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.302ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q i2c_slave_inst0/cycle_pulse (from clk_sys +)
Destination: FF Data in i2c_slave_inst0/sr[1] (to clk_sys +)
FF i2c_slave_inst0/sr[0]
Delay: 0.278ns (47.8% logic, 52.2% route), 1 logic levels.
Constraint Details:
0.278ns physical path delay i2c_slave_inst0/SLICE_402 to SLICE_1146 meets
-0.024ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.024ns) by 0.302ns
Physical Path Details:
Data path i2c_slave_inst0/SLICE_402 to SLICE_1146:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R13C6D.CLK to R13C6D.Q0 i2c_slave_inst0/SLICE_402 (from clk_sys)
ROUTE 9 0.145 R13C6D.Q0 to R13C6C.CE i2c_slave_inst0/cycle_pulse (to clk_sys)
--------
0.278 (47.8% logic, 52.2% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to i2c_slave_inst0/SLICE_402:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R13C6D.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_1146:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R13C6C.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.302ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q fan2_ctrl/clk_pwm_en (from clk_sys +)
Destination: FF Data in fan2_ctrl/counterPWM1[7] (to clk_sys +)
Delay: 0.278ns (47.8% logic, 52.2% route), 1 logic levels.
Constraint Details:
0.278ns physical path delay fan2_ctrl/SLICE_356 to fan2_ctrl/SLICE_26 meets
-0.024ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.024ns) by 0.302ns
Physical Path Details:
Data path fan2_ctrl/SLICE_356 to fan2_ctrl/SLICE_26:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R13C17C.CLK to R13C17C.Q0 fan2_ctrl/SLICE_356 (from clk_sys)
ROUTE 11 0.145 R13C17C.Q0 to R13C17A.CE fan2_ctrl.clk_pwm_en (to clk_sys)
--------
0.278 (47.8% logic, 52.2% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to fan2_ctrl/SLICE_356:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R13C17C.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to fan2_ctrl/SLICE_26:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R13C17A.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q bios_sel_dly[0] (from clk_sys +)
Destination: FF Data in bios_sel_dly[1] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_265 to SLICE_265 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_265 to SLICE_265:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R11C11C.CLK to R11C11C.Q0 SLICE_265 (from clk_sys)
ROUTE 1 0.152 R11C11C.Q0 to R11C11C.M1 bios_sel_dly[0] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_265:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R11C11C.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_265:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R11C11C.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q com_exp_ctrl_inst1/pwrbtn_tri_r[0] (from clk_sys +)
Destination: FF Data in com_exp_ctrl_inst1/pwrbtn_tri_r[1] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_324 to SLICE_324 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_324 to SLICE_324:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R11C6B.CLK to R11C6B.Q0 SLICE_324 (from clk_sys)
ROUTE 1 0.152 R11C6B.Q0 to R11C6B.M1 com_exp_ctrl_inst1/pwrbtn_tri_r[0] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_324:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R11C6B.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_324:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R11C6B.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q i2c_slave_inst0/ram_clken_r4_0 (from clk_sys +)
Destination: FF Data in i2c_slave_inst0/ram_clken_r5 (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_438 to SLICE_442 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_438 to SLICE_442:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C11C.CLK to R5C11C.Q1 SLICE_438 (from clk_sys)
ROUTE 1 0.152 R5C11C.Q1 to R5C11D.M1 i2c_slave_inst0/ram_clken_r4_0 (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_438:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R5C11C.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_442:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R5C11D.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q i2c_slave_inst0/ram_clken_r7 (from clk_sys +)
Destination: FF Data in i2c_slave_inst0/ram_clken_r8 (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_446 to SLICE_448 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_446 to SLICE_448:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R9C7C.CLK to R9C7C.Q1 SLICE_446 (from clk_sys)
ROUTE 1 0.152 R9C7C.Q1 to R9C7D.M1 i2c_slave_inst0/ram_clken_r7 (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_446:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R9C7C.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_448:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R9C7D.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q i2c_slave_inst0/ram_clken_r8 (from clk_sys +)
Destination: FF Data in i2c_slave_inst0/ram_clken_r9 (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_448 to SLICE_451 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_448 to SLICE_451:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R9C7D.CLK to R9C7D.Q1 SLICE_448 (from clk_sys)
ROUTE 1 0.152 R9C7D.Q1 to R9C7B.M1 i2c_slave_inst0/ram_clken_r8 (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_448:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R9C7D.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_451:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R9C7B.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q psu_ok_r[0] (from clk_sys +)
Destination: FF Data in psu_ok_r[1] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_494 to SLICE_494 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_494 to SLICE_494:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C16C.CLK to R5C16C.Q0 SLICE_494 (from clk_sys)
ROUTE 1 0.152 R5C16C.Q0 to R5C16C.M1 psu_ok_r[0] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_494:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R5C16C.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_494:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R5C16C.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm75_int4_dly[0] (from clk_sys +)
Destination: FF Data in lm75_int4_dly[1] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_860 to SLICE_860 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_860 to SLICE_860:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C11D.CLK to R4C11D.Q0 SLICE_860 (from clk_sys)
ROUTE 1 0.152 R4C11D.Q0 to R4C11D.M1 lm75_int4_dly[0] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_860:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R4C11D.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_860:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R4C11D.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q cb_rst_tmp[0] (from clk_sys +)
Destination: FF Data in cb_rst_tmp[1] (to clk_sys +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_864 to SLICE_864 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_864 to SLICE_864:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C11B.CLK to R3C11B.Q0 SLICE_864 (from clk_sys)
ROUTE 1 0.152 R3C11B.Q0 to R3C11B.M1 cb_rst_tmp[0] (to clk_sys)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_864:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R3C11B.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to SLICE_864:
Name Fanout Delay (ns) Site Resource
ROUTE 553 1.416 OSC.OSC to R3C11B.CLK clk_sys
--------
1.416 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_sys" 66.500000 MHz ; | 0.000 ns| 0.302 ns| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: clk_sys Source: OSCH_inst.OSC Loads: 553
Covered under: FREQUENCY NET "clk_sys" 66.500000 MHz ;
Data transfers from:
Clock Domain: COME_CPLD_LPC_CLK_c Source: COME_CPLD_LPC_CLK.PAD
Not reported because source and destination domains are unrelated.
Clock Domain: COME_CPLD_LPC_CLK_c Source: COME_CPLD_LPC_CLK.PAD Loads: 29
No transfer within this clock domain is found
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 18134 paths, 1 nets, and 7056 connections (80.13% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
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