Map TRACE Report
Loading design for application trce from file m0_cpld_v25_impl1_map.ncd.
Design name: Belgite_BOARD_CPLD
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-2000HC
Package: FTBGA256
Performance: 4
Loading device for application trce from file 'xo2c2000.nph' in environment: E:/lattice 3.12/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Wed Dec 08 15:54:00 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o M0_CPLD_V25_impl1.tw1 -gui -msgset E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_aa/promote.xml M0_CPLD_V25_impl1_map.ncd M0_CPLD_V25_impl1.prf
Design file: m0_cpld_v25_impl1_map.ncd
Preference file: m0_cpld_v25_impl1.prf
Device,speed: LCMXO2-2000HC,4
Report level: verbose report, limited to 1 item per preference
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Preference Summary
FREQUENCY NET "clk_sys" 66.500000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
Report: 71.068MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY NET "clk_sys" 66.500000 MHz ;
4096 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 0.967ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q s_i2c_wr_dly[0] (from clk_sys +)
Destination: FF Data in cnt_300s[8] (to clk_sys +)
FF cnt_300s[7]
Delay: 13.789ns (28.4% logic, 71.6% route), 8 logic levels.
Constraint Details:
13.789ns physical path delay SLICE_524 to SLICE_122 meets
15.038ns delay constraint less
0.282ns CE_SET requirement (totaling 14.756ns) by 0.967ns
Physical Path Details:
Data path SLICE_524 to SLICE_122:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 SLICE_524.CLK to SLICE_524.Q0 SLICE_524 (from clk_sys)
ROUTE 5 e 1.234 SLICE_524.Q0 to SLICE_931.A0 s_i2c_wr_dly[0]
CTOF_DEL --- 0.495 SLICE_931.A0 to SLICE_931.F0 SLICE_931
ROUTE 4 e 1.234 SLICE_931.F0 to */SLICE_984.D1 s_i2c_wr_en
CTOF_DEL --- 0.495 */SLICE_984.D1 to */SLICE_984.F1 LPC_IO_Cycle_Inst/SLICE_984
ROUTE 3 e 1.234 */SLICE_984.F1 to */SLICE_988.A1 LPC_IO_Cycle_Inst/N_879
CTOF_DEL --- 0.495 */SLICE_988.A1 to */SLICE_988.F1 LPC_IO_Cycle_Inst/SLICE_988
ROUTE 2 e 1.234 */SLICE_988.F1 to */SLICE_993.A0 LPC_IO_Cycle_Inst/N_1605_1
CTOF_DEL --- 0.495 */SLICE_993.A0 to */SLICE_993.F0 LPC_IO_Cycle_Inst/SLICE_993
ROUTE 2 e 1.234 */SLICE_993.F0 to */SLICE_980.A0 LPC_IO_Cycle_Inst/N_3102
CTOF_DEL --- 0.495 */SLICE_980.A0 to */SLICE_980.F0 LPC_IO_Cycle_Inst/SLICE_980
ROUTE 2 e 1.234 */SLICE_980.F0 to */SLICE_973.A1 LPC_IO_Cycle_Inst/cnt_300s_1_sqmuxa_i_0_o2_2
CTOF_DEL --- 0.495 */SLICE_973.A1 to */SLICE_973.F1 LPC_IO_Cycle_Inst/SLICE_973
ROUTE 3 e 1.234 */SLICE_973.F1 to SLICE_470.C1 LPC_IO_Cycle_Inst/fan1_pwm_ctrl_reg9_0_a2_RNI3IDI3
CTOF_DEL --- 0.495 SLICE_470.C1 to SLICE_470.F1 SLICE_470
ROUTE 5 e 1.234 SLICE_470.F1 to SLICE_122.CE cnt_300se (to clk_sys)
--------
13.789 (28.4% logic, 71.6% route), 8 logic levels.
Report: 71.068MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_sys" 66.500000 MHz ; | 66.500 MHz| 71.068 MHz| 8
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: clk_sys Source: OSCH_inst.OSC Loads: 553
Covered under: FREQUENCY NET "clk_sys" 66.500000 MHz ;
Data transfers from:
Clock Domain: COME_CPLD_LPC_CLK_c Source: COME_CPLD_LPC_CLK.PAD
Not reported because source and destination domains are unrelated.
Clock Domain: COME_CPLD_LPC_CLK_c Source: COME_CPLD_LPC_CLK.PAD Loads: 29
No transfer within this clock domain is found
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 18134 paths, 1 nets, and 7056 connections (80.13% coverage)
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Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
Wed Dec 08 15:54:01 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o M0_CPLD_V25_impl1.tw1 -gui -msgset E:/work/CPLD_Program/M0/DVT_pro/M0_CPLD_V25_aa/promote.xml M0_CPLD_V25_impl1_map.ncd M0_CPLD_V25_impl1.prf
Design file: m0_cpld_v25_impl1_map.ncd
Preference file: m0_cpld_v25_impl1.prf
Device,speed: LCMXO2-2000HC,M
Report level: verbose report, limited to 1 item per preference
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Preference Summary
FREQUENCY NET "clk_sys" 66.500000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "clk_sys" 66.500000 MHz ;
4096 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 0.351ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q i2c_slave_inst0/sr[2] (from clk_sys +)
Destination: FF Data in i2c_slave_inst0/sr[3] (to clk_sys +)
Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
Constraint Details:
0.332ns physical path delay SLICE_1027 to SLICE_1027 meets
-0.019ns M_HLD and
0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
Physical Path Details:
Data path SLICE_1027 to SLICE_1027:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 SLICE_1027.CLK to SLICE_1027.Q0 SLICE_1027 (from clk_sys)
ROUTE 4 e 0.199 SLICE_1027.Q0 to SLICE_1027.M1 i2c_slave_inst0/sr[2] (to clk_sys)
--------
0.332 (40.1% logic, 59.9% route), 1 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_sys" 66.500000 MHz ; | 0.000 ns| 0.351 ns| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: clk_sys Source: OSCH_inst.OSC Loads: 553
Covered under: FREQUENCY NET "clk_sys" 66.500000 MHz ;
Data transfers from:
Clock Domain: COME_CPLD_LPC_CLK_c Source: COME_CPLD_LPC_CLK.PAD
Not reported because source and destination domains are unrelated.
Clock Domain: COME_CPLD_LPC_CLK_c Source: COME_CPLD_LPC_CLK.PAD Loads: 29
No transfer within this clock domain is found
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 18134 paths, 1 nets, and 7056 connections (80.13% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
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