ODSA sub-project held its 3rd workshop at the Intel Santa Clara campus on June 10, 2019 - Topline Summary

The OCP’s ODSA sub-project held its 3rd workshop at the Intel Santa Clara campus on June 10, 2019. Interest in the ODSA workgroup is growing. The workshop was sold out, with more than 150 registrants from over 65 companies and the agenda featured 29 speakers from 19 companies. The topics covered included an overview of chiplet development, progress on the ODSA protocol stack and panels on practical design experience and workflow with chiplets. The slides and video for the talks are available at the ODSA wiki. The presentations are reviewed briefly below.


The workshop opened with well-received talks from management and senior engineers at Intel. Ahmad Zaidi, VP and GM Chipsets and IP Technologies Group and the executive sponsor for the event, welcomed the attendees. Senior Principal Engineer Ramune Nagisetty opened with a broad overview of chiplet development at Intel, products that integrated multiple chips, the motivation for chiplets and the path to an open ecosystem. Nagisetty’s talk closed with two announcements in support of an open ecosystem, one of which was a PIPE interface, compatible with the ODSA stack, for short-reach on-package off-die communication and the second on support for an open power modeling standard. Audience questions included practical details on the products discussed in the talk and details on the new short-reach PIPE interface. Animesh MIshra and Robbie Adler presented a platform, aimed at easing composability, integration, validation and software development for chiplet-based products.


The second session was organized around progress on the ODSA protocol stack. The author (of this post) presented a technical introduction and an overview of ODSA milestones - call for papers (based on work by the group) accepted at Hot Interconnect, a new survey on chiplet physicals and progress on the Prototype. Feedback from the audience centered around simplifying the stack. Ramin Farjadrad from Aquantia and Mark Kuemerle from Avera Semi presented an update on the ODSA Bunch of Wires (BoW) interface proposal. Highlights include a control interface compatible with the Intel AIB and a call for open source implementations with foundry support. Attendees asked for more performance data that included substrate effects, such as crosstalk. David Kehlet from Intel presented a detailed introduction to the open AIB bus from Intel. Kehlet asserted that advanced packaging technology is triggering the growth in multi-chiplet products. Kehlet also issued a call for cooperation on defining the link and higher layers in the ODSA stack. One significant question from the audience was on whether Intel would also open up the packaging technology needed with the AIB for third-party use. The session closed with a presentation from Surya Bhattacharya from the Institute of Microelectronics in Singapore. Bhattacharya walked through the advanced packaging technologies demonstrated and available and invited collaboration in prototyping for advanced devices.


The afternoon session opened with a panel on practical design experience with chiplets. Ramune Nagisetty moderated the panel and the participants were Gabe Loh from AMD, Sanjeev Joshi from CIsco, Carlos Macian from eSilicon, Dave Kehlet from Intel and Sagheer Ahmad from Xilinx. The panel covered topics ranging from architecture,  implementation, to business issues. Some interesting points made by the panelists included: Interoperability may be easier than reuse; I/O is highest on the wishlist for delivery as chiplets; Chiplets make multiple SKUs easier; Systems vendors are interested in open interfaces between chiplets; An open system requires a lot of progress (of course); Chiplets may be easier to implement for a large company with lots of products than across companies; Security is an important challenge with open architectures.


As mentioned in several talks and in the panel, open chiplets require companies to share substantial (normally confidential) information about chiplet physicals. Using the results of a new survey conducted by the ODSA, Jawad Nasrullah from zGlue and Alex Wright-Gladstein from Ayar Labs showed that management in the chiplet ecosystem was ready for sharing this type of information. Nasrullah proposed that zGlue’s ZEF format be used as a starting point for the specification. The first session concluded with a presentation by Eugene Chow from Xerox PARC on advanced packaging technologies, similar to laser printing, for massive arrays of chiplets. A second part of Chow’s talk suggested using MEMS spring mounts to attach chiplets to a substrate to easily remove defective die in a multi-chiplet package.


The last session of the workshop started with a panel on workflow with chiplets. Sam Fuller from NXP moderated the panel and the participants were Wolfgang Sauter from Avera Semi, Alex Wright-Gladstein from Ayar Labs, Halil Cirit from Facebook, Vamshi Kandalla from Granite River Labs and Brian Holden from Kandou. Some interesting insights from this panel: Packaging and test are now early factors in design decisions; Routing flexibility for inter-chiplet interconnect could be very useful in package design; Device disaggregation can potentially relax design requirements.


The day ended with a report out from the ODSA prototype design team on a new disaggregated design flow for the prototype design, a schedule for development and a list of volunteer asks from the community.


The OCP thanks Intel for hosting the workshop, in particular Animesh Mishra and Cynthia Cobb. Intel was generous in sponsoring both the venue and providing food and refreshments for the breaks.


The summer promises to be a busy time for the ODSA project. Two papers based on work from the group will be presented at the Hot Interconnect workshop, also hosted at Intel, in August, 2019. We are currently planning our next ODSA workshop for August. The ODSA also has a session and a panel at the OCP Regional Summit in Amsterdam in September. We anticipate reporting significant progress on the PHY layer, BoW interface, CDX and Prototype at these events while continuing to leverage the expertise of the design and packaging communities.


Video from the ODSA workshop is up: https://www.youtube.com/watch?v=-LA4fj0KTYg&feature=youtu.be


For video and slides: https://www.opencompute.org/events/past-events