Editing Server/DC-MHS
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*M-DNO: [mailto:dirk.blevins@intel.com Dirk Blevins] (Intel) and [mailto:michael.gregoire@dell.com Michael Gregoire] (Dell) | *M-DNO: [mailto:dirk.blevins@intel.com Dirk Blevins] (Intel) and [mailto:michael.gregoire@dell.com Michael Gregoire] (Dell) | ||
*M-XIO/PESTI: [mailto:charlie.ziegler@dell.com Charlie Ziegler] (Dell) and [mailto:javier.lasa@intel.com Javier Lasa] (Intel) | *M-XIO/PESTI: [mailto:charlie.ziegler@dell.com Charlie Ziegler] (Dell) and [mailto:javier.lasa@intel.com Javier Lasa] (Intel) | ||
*M-PIC: [mailto:tim.lambert@dell.com Tim Lambert] (Dell) | *M-PIC: [mailto:tim.lambert@dell.com Tim Lambert] (Dell) and [mailto:clifford.h.dubay@intel.com Cliff DuBay] (Intel) | ||
*M-CRPS: [mailto:aurelio.rodriguez.echevarria@intel.com Aurelio Rodriguez Echevarria] (Intel) and [mailto:jon.lewis@dell.com Jon Lewis] (Dell) | *M-CRPS: [mailto:aurelio.rodriguez.echevarria@intel.com Aurelio Rodriguez Echevarria] (Intel) and [mailto:jon.lewis@dell.com Jon Lewis] (Dell) | ||
*M-SIF: [mailto:dirk.blevins@intel.com Dirk Blevins] (Intel) and [mailto:gregory.sellman@amd.com Greg Sellman] (AMD) | *M-SIF: [mailto:dirk.blevins@intel.com Dirk Blevins] (Intel) and [mailto:gregory.sellman@amd.com Greg Sellman] (AMD) | ||
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*M-PnP: [mailto:tim.lambert@dell.com Tim Lambert] (Dell) and [mailto:phillip.leech@hpe.com Phil Leech] (HPE) | *M-PnP: [mailto:tim.lambert@dell.com Tim Lambert] (Dell) and [mailto:phillip.leech@hpe.com Phil Leech] (HPE) | ||
*Edge-MHS: [mailto:dirk.blevins@intel.com Dirk Blevins] (Intel), [mailto:jayesh@amperecomputing.com Jayesh Shah] (Ampere), and [mailto:rodion.naurzalin@hpe.com Rodion Naurzalin] (HPE) | *Edge-MHS: [mailto:dirk.blevins@intel.com Dirk Blevins] (Intel), [mailto:jayesh@amperecomputing.com Jayesh Shah] (Ampere), and [mailto:rodion.naurzalin@hpe.com Rodion Naurzalin] (HPE) | ||
==Current Status== | ==Current Status== |